Tuesday, 2019-04-02

*** tpb has joined #vtr-dev00:00
litghostkem_: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/52401:20
tpbTitle: Wire length metric incorrectly terminates routing iterations · Issue #524 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)01:20
litghostkem_: I've seen at least one case where VPR generated an "antenna" net, e.g. a route that enters a channel but never leaves it16:03
litghostkem_: I consider this behavior suprising, possible bug?16:03
litghostkem_: This is using switches with mux's and short's, so adding the "antenna" net shouldn't modify timing because the isolation of the mux switch16:04
kem_litghost: You mean effectively a 'stub' branch of the route tree which doesn't connect to any sink?16:06
litghostkem_: Yes16:07
kem_litghost: If the driver of that wire is configurable (i.e. a mux) then yes that would be unexpected16:07
litghostkem_: Okay, later today I'll write up a bug with the arch and graph16:08
mithrokem_: Would you be free tomorrow morning to look at landing some of the formatting changes for the EXTERNAL libs?16:27
litghostkem_: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/52618:35
tpbTitle: Router generating "stub" or "antenna" nets · Issue #526 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)18:35
litghostkem_: I might be missing something, but I'm relatively confident this is a real issue18:36

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