Tuesday, 2018-07-31

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mithrokem_: Welcome back! :-)19:03
kem_mithro: Thanks, I'm back for a couple days this week and more fully next week.19:24
kem_mithro: Seems like you have been making good progress on ice40 in the mean time19:24
mithroNeed some advice on things, so probably good to chat sometime in the next couple of days19:26
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kem_mithro: Sure, either tomorrow or next week should work20:40
mithrokem_: The two major questions I have are20:42
mithro(a) What is the correct way to figure out if a mux interconnect is being used -- the best I have come up with is https://github.com/mithro/vtr-verilog-to-routing/blob/without-packing-changes/vpr/src/util/ice40_hlc.cpp#L491-L545 so far but I'm still getting a couple of cases were an interconnect is being marked as used but shouldn't be (when comparing to the xxx.net file)20:45
tpbTitle: vtr-verilog-to-routing/ice40_hlc.cpp at without-packing-changes · mithro/vtr-verilog-to-routing · GitHub (at github.com)20:45
mithro(b) I still don't understand how to do carry-chain pack-patterns -- is it possible to actually use multiple carry primitives chained together inside one tile?20:46
mithroWhen I dig into it, the packer seems very confused by the lack of path from the carry out onto the general fabric and this is without the extra mux that confuses it otherwise21:17
mithroI'll chat with you about it more tomorrow21:17
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