Wednesday, 2018-07-11

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digshadowelms, mithro: was able to get a up5k design fully through the perf tool pipeline00:02
digshadow(using vpr)00:02
mithrodigshadow: Awesome!00:03
digshadowalso I'm noticing that the radiant strategy option seems to be ignored, not sure if thats worth looking into00:05
digshadowat least for simple designs. Maybe once I throw an SoC in it will do something more interesting00:05
mithrodigshadow: Sounds pretty normal :-P00:05
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mithrokem_: Random question for you
tpbTitle: Why does VPR prevent clock driving both data and clock pins? · Issue #375 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
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mithrokem_: Morning! Hope those papers are going well15:47
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