Thursday, 2018-07-05

*** tpb has joined #vtr-dev00:00
mithrokem_: any feedback on this proposed format change to the port specification format?17:35
tpbTitle: Snippet | IRCCloud (at
mithrokem_: The big thing I'm trying to achieve with that change is to not have the name of the blocks repeated in the port specifications (so that things are easier to compose)17:36
mithrokem_: I currently have a xslt script which transform this format to the existing format17:37
mithrodaveshah: With the above change it makes it very easy to do the xinclude stuff I mentioned above17:41
*** eddieh has joined #vtr-dev17:51
eddiehHowdy do18:30
* eddieh hasn't used IRC for a loooong time18:30
daveshaheddieh: hey18:30
eddiehOoh it still works18:30
eddiehSo until recently I thought VTR was something that fell out of favour... at least from the academic side18:33
eddiehTo be overtaken by these new-fangled "HLS", "ML", etc. buzzwords18:34
eddiehBut now I'm excited to learn that doesn't appear to be the case!18:35
mithrohey eddieh :-)19:43
mithrojohn is digshadow19:43
mithroeddieh: I'll be back in about an hour, just going to lunch now19:43
digshadowhey eddieh!20:23
digshadowhehe I see I bullied you enough to show up :)20:23
eddiehhello indeed! I feel like I need a cool pseudonym too20:37
*** eddieh is now known as heddie20:47
mithroheddie: So, I'm currently concentrating on vtr for ice4020:50
mithroheddie: We have blinky working and elms is looking at the blockram20:52
heddiesounds good20:52
mithroheddie: Then we will go back to doing artix-720:53
heddieI have no experience working with lattice20:53
mithroheddie: Artix-7 is really just waiting on me finishing the rr_graph generation20:53
heddieBut I have VTR-to-Bits "working" for V6 and Artix7 zc702020:54
mithroheddie: I have a python script which prints the rr_graph in human form20:54
heddieMy approach is encumbered by the use of XDLRC, though20:54
mithroheddie: We have taken the approach of having a Python library for generating the rr_graph20:55
mithroheddie: mapping real fabric to the rr_graph format has a bit of impedance mismatch, but the Python library kind of "papers over" a lot of it20:57
heddieAs I'm sure you know VPR procedural generates the routing graph in order to support architecture exploration20:57
mithroheddie: Yes - but it can now load an xml file with the routing20:57
mithroheddie: I believe it might have been added after your VtB work20:58
heddieHowever, mapping to a real architecture, will all its nooks, crannies, and exceptions means it was painful to teach it to account for those exceptions20:58
heddieYes, that is new to me20:58
mithroheddie: Dunno /how/ new that stuff is20:59
heddieI recall the UoT people were talking about doing it20:59
heddieThis was in 2015, after which I lost touch with this area20:59
mithroheddie: Well, they did it sometime between your work and the time we started working20:59
mithroheddie: FYI - Our "architecture definitions" can be found at
tpbTitle: GitHub - SymbiFlow/symbiflow-arch-defs: FOSS architecture definitions of FPGA hardware useful for doing PnR device generation. (at
mithroheddie: We are moving towards generating all the VPR XML configuration from specially annotated Verilog simulation models21:00
mithroheddie: I'm also hoping to auto generate graphics and documentation from these sim models too21:01
heddieSounds like a decent approach21:02
mithroheddie: We also make heavy use of XML includes to make it easier for composible21:03
heddieMy biggest concern would be how exceptions are handled21:03
heddieat boundaries, across holes in the fabric, etc.21:03
mithroheddie: Will be interesting to see how far we can push it21:04
heddieI also expect there to be some discrepancies between logical layout and physical timing21:05
heddiewith not all timing arcs being the same21:05
mithroheddie: I have a example of my thinking about fabric ->
tpbTitle: Proposal for alternative fabric and switch specification format · Issue #286 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
mithroheddie: Playing with that idea here ->
tpbTitle: symbiflow-arch-defs/ at 77fdf28c1227a2e92e03132c43a54ea5023e18f1 · mithro/symbiflow-arch-defs · GitHub (at
heddieLooks interesting!21:09
heddieI of course took the easy approach and just generated a binary blob to be slurped into memory21:09
mithroheddie: I'm thinking about a flat buffer based replacement for the rr_graph in the future -- but the XML isn't a huge blocking factor, it's more getting things actually working21:11
mithroheddie: Even like 2g of XML only takes a second to load21:12
heddieBut then that begs the question of why slurp in a massive XML only to have to process it from human-readable to binary?21:13
mithroheddie: being able to open the file in a text editor has been rather helpful21:14
heddieNot to sound like I'm on the attack, just trying to understand what your thought pattern is21:14
mithroheddie: And VtR already had the rr_graph xml support, so the least amount of change to VtR21:15
heddieIndeed, but it sounds like XML is the middle man that's generated from a python script21:15
mithroheddie: Yeap, and probably go away in the future -- but for a temporary solution it is "good enough"21:16
mithroperfect is the enemy of ever getting anything done :-P21:16
heddiea very fair comment!21:16
mithroheddie: The goal is to get something which can do PicoSoC and then go back and improve the tooling21:18
mithroit's much easier to understand the correct approach for the tooling once you have something which works :-P21:20
mithrowe are also have been focused on "proving what is possible" rather then "doing it the best way"21:22
heddieNot to toot my own horn, would the approach taken by VTR-to-Bitstream tick the "it's possible" box?21:23
heddieMinus bitgen21:23
heddieBut is XDLRC considered polluting?21:24
mithroheddie: I don't think I recall you publishing anything for the Series 7?21:24
heddieNo, it's in my github21:24
heddieThe same XDLRC can be applied to any ISE family21:25
heddieThe same XDLRC *approach* can be applied to any family supported by ISE21:25
mithroXDLRC requires the vendor tools?21:25
mithroIt's been quite a long time since I last looked at VtB21:26
mithroheddie: Our goal was to prove you could do it *without* vendor tools21:26
heddieXDLRC step is a one-off procedure that converts the info provided by vendor tools into a pre-generated rr_graph binary array21:26
heddie(I use Torc to access that XDLRC data)21:27
heddieI made a modification to VPR to load in that rr_graph binary blob and put it exactly where the procedurally generated result would otherwise be21:27
heddieThe only step I need vendor tools for (and a license for non webpack devices) is bitgen21:29
mithroheddie: Yeah - we wanted to be able to generate something we can load on a FPGA without touching the vendor tools at all21:30
mithroIE No bitgen either21:30
heddieThat last step wasn't particularly interesting to me as it gave me nothing new21:31
daveshahheddie: did you hear about the Rapidwright business recently?21:31
heddiePlus it was known to be a legally gray area...21:31
heddieHi Dave. Yes, I learned that from Clifford when I saw him at DAC21:31
heddieWould love to know the story behind that21:32
daveshahYeah, it was very odd.21:32
daveshahI've had a bit of contact with Xilinx about this stuff because the asked me to remove my fork but didn't get a reason21:32
heddieI reached out to someone close to the author and they didn't know much more... yet21:33
daveshahI think they want to release it in a more binary blobified form21:33
daveshahBut have to sort out gpl dependencies21:33
heddieThat's a more promising result than I thought it would be21:33
daveshahInterestingly, Lattice Diamond has a lot of similar low level interfaces to ISE (because they share NeoCAD routes) although even less documented21:34
daveshahI have used them extensively for my ECP5 fuzzing21:34
daveshahThey have ncl (NeoCAD listing) which is quite similar to xdl21:34
heddieI have zero experience with lattice21:36
heddieThe research labs I was in were all Xilinx/Altera devices21:36
daveshahYeah, Lattice have a pretty low presence in unis (except those using icestorm for intro teaching :D)21:37
daveshahECP5 are pretty nice parts, particularly considering pricing21:38
heddieFair enough! Never had to go out and buy one myself21:44

Generated by 2.13.1 by Marius Gedminas - find it at!