Tuesday, 2018-06-19

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mithrokem_/elms: I think https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/368 is blocking us getting the blockram working on a real iCE4004:34
tpbTitle: Floating point exception in get_bidir_opin_connections with multi-tile blocks · Issue #368 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)04:34
mithroelms: FYI -> https://docs.google.com/document/d/1kTehDgse8GA2af5HoQ9Ntr41uNL_NJ43CjA32DofK8E/edit#heading=h.qwbbqhhq91qi04:34
tpbTitle: VPR and iCE40 Information - Google Docs (at docs.google.com)04:34
elmsmithro: thanks. Image is still looking like a lot of progress.04:35
mithroelms: the yellow to grey routing is broken04:40
mithroelms: so nothing routes at the moment04:41
mithroThe placement is also quite weird04:44
mithroBut the packing seems to be really decent04:44
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kem_mithro: I thought the conclusion was that iCE40 was actually a unidir architecture? In which case you shouldn't need the (broken) bidir RR graph generator?13:12
daveshahkem_: yep, the iCE40 only has unidir switches - but unlike the ECP5 for example, internal signals still have more than one possible driver so I don't know whether it counts as a fully unidir architecture13:14
kem_daveshah: What does 'internal signal' mean? Internal to the logic blocks?13:17
daveshahkem_: no, interblock span wires13:17
daveshahi.e. there is more than one place to route a signal onto a span wire, IIRC13:17
daveshahwhereas in the ECP5, each span wire has exactly one driver and two loads, so is much simpler, for example13:17
daveshaheffectively, the architecture switches tend to be a mux followed by a tristate driver with one bit in the bitstream controlling "enable" (there is no runtime switchable tristate stuff internally)13:19
kem_daveshah: OK thanks  for clarifying, that's making more sense now13:21
daveshahkem_: inside the official tools, there are actually two types of switches. "buffer" and "routing". We inherited the incorrect assumption that "routing" switches were bidirectional, but they are both unidirectional. The actual difference seems to be the bit patterns and nothing else...13:22
mithrokem_: it doesn't have pass_gates, but does have bidirectional wires14:58
kem_mithro: Got it. FYI the FPE bug should be fixed.14:59
mithrokem_: thanks!14:59
mithrokem_: Really appreciate the fast fixes!16:18
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