Sunday, 2018-06-10

*** tpb has joined #vtr-dev00:00
tpbTitle: How to model "mutually exclusive" fan out in a rr_graph.xml · Issue #351 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
daveshahif it's any consolation, this wasted most of Clifford and my days...15:09
mithrodaveshah: interesting20:34
daveshahmithro: arachne-pnr actually marks these as bidir in its routing graph, but fortunately ignores that due to an omission in the router!20:36
daveshahAnyway, it looks like everything in the ice40 is unidir so that issue can be closed, although I may poke about a bit to make absolutely sure20:37
mithrodaveshah: well that makes things a lot easier20:41
mithroWhat made you look at it again?20:41
daveshahSuch discussions are beyond my pay grade :P20:41
mithroWell it seems like I have logic equivalence working for VtR on the blif and Verilog output20:48
mithroSo the problem must be in my HLC output or the HLC conversion20:49
daveshahmithro: my feeling is its in the LUT rotation20:50
daveshahor possibly auto generated pass through LUTs20:50
daveshahBut good to know its not a core vpr issue20:50
mithroMy feeling too20:50
daveshahFor the former, feels like a case of pencil and paper debugging would be best20:50
mithroBut i'm struggling with not really knowing how the LUT init bits work20:51
daveshahIt is simply a 16 bit ROM20:53
daveshahConcatenate the inputs together, I0 as LSB, and use that as an index20:53
mithroI also know pretty much were things are broken20:53
mithroThe Sim target shows exactly which signals are involved20:54
daveshahmithro: this might help more?
tpbTitle: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at
daveshahYeah, should be possible to find the same lut in the official netlist and compare20:55
mithrodaveshah: it would be really nice if the bitstream to Verilog generated LUTs instead of the weird try states it does20:57
daveshahmithro: for now, have a look at the icestorm_explain output for LUT values20:58
daveshahI think icetime might produce a Verilog netlist with LUTs too, but I haven't tried20:58
mithroBe back in 2020:58
daveshahicebox_vlog does what it does to produce a functional netlist that is platform independent and works anywhere without being too large20:59
mithroSo now it's "This section lists the routing configuration bits in the tile. All routing resources are directional tristate buffers that are in tristate mode in the all-zeros configuration. "21:23
daveshahmithro: Yeap21:25
daveshahProbably worth eliminating the bidirectional stuff from HLC too21:25
mithrodaveshah: Does this look right?21:28
tpbTitle: Ubuntu Pastebin (at
daveshahAlso let me know if you see references to bidirectional switches anywhere else in ice40/icestorm stuff so I can remove them21:28
mithrodaveshah: Specifically the in_0 / in_3 / in_1 luts?21:28
daveshahmithro: they look the wrong way round in the normal order21:29
daveshahIf that is MSB first21:29
daveshahI think it's LSB first though, then it's fine21:30
mithrodaveshah: It's the format HLC uses internally....21:30
daveshahThat's what icebox_explain uses21:30
daveshahNo idea what HLC uses21:30
mithroThe stuff below is what icebox explain uses21:30
daveshahBut the Verilog models are MSB first, so be careful21:30
daveshahI think HLC and icebox_explain are the same21:31
daveshahSo it's fine21:31
daveshahBut IMO putting 16'b before somethint makes it look like it should be MSB first, which is confusing21:31
mithrodaveshah: But then I'm outputing them in the wrong order I think....21:32
daveshahI don't know what VPR uses internally21:33
daveshahI would expect nothing to work correctly if they were the wrong way round21:33
daveshahI'm fairly certain your ordering is correct, but a bit confusing21:33
mithrodaveshah: Yeah - I would expect all my lut tests to fail21:34
daveshahI would probably remove the 16'b prefix in HLC. Then it is clear it is in icebox_explain, LSB first order.21:35
mithro['out', '=', "16'b0010000000000000"] 001000000000000021:37
mithroThat looks wrong for a route-through-in1 ?21:37
daveshahYes, that's not right at all21:37
mithroYet it seems to pass equivalence checking?21:38
daveshahSorry, its fine actually21:38
daveshahAll the other inputs are 021:39
daveshahThat truth table implies output is high when the inputs are equal to 2 (0b0010)21:39
mithrodaveshah: ['out', '=', 'in_1'] 001100110011001121:40
daveshahEqually valid solutions21:40
daveshahThe former only works when all other inputs are zero, but that is the case in hardware if they are not driven21:40
mithrodaveshah: The first one?21:41
daveshahYeah, but both should work21:41
daveshahI know 010000... works as a pass through for in021:42
tpbTitle: Snippet | IRCCloud (at
daveshahThat should produce something like 0000 0000 1000 000021:44
daveshahIf inputs are not rotated21:44
daveshahIf they are, there should still only be one 1 but in a different position21:44
daveshahAnyway, bed for me now21:46
tpbTitle: Ubuntu Pastebin (at
mithrodaveshah: Your right about the icetime output being easier to look at21:52

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