Saturday, 2018-06-09

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mithrokem_: so, I should be able to use --gen_post_synthesis_netlist to check logical equivalence?01:50
kem_mithro: Yep, we use ABC to do LEC in our regression tests01:52
kem_mithro: See for instance:
tpbTitle: vtr-verilog-to-routing/config.txt at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
mithrokem_: I'm trying to figure out why my output .hlc file is not logically equivalent to my input01:53
kem_mithro: Since we do regression test it VPR's output *should* be correct01:53
kem_mithro: But probably worth verifying on your architecture/circuit combination01:54
kem_mithro: Just to be safe :)01:54
mithrokem_: I'm pretty sure it is something in my hlc output code -- but can't find it...01:54
mithrokem_: So am double checking everything else :-P01:54
mithrokem_: Is there a way to get the blif after packing?01:56
kem_mithro: --gen_post_synthesis_netlist on should dump blif and verilog01:57
mithrokem_: So when using --gen_post_synthesis_netlist I get "Message: Primitive 'SB_LUT4' not recognized by netlist writer"01:57
kem_mithro: Ah, it probably only supports the standard BLIF plus some of VTR's standard primitives01:59
mithrokem_: Yeah -- it doesn't seem to support black boxes?02:00
kem_mithro: It supports a hard-coded list of blackboxes... but not blackboxes in general02:00
mithrokem_: Is there a way to set the gen_post_synthesis_netlist format?02:01
kem_mithro: It always dumps BLIF, Verilog and an SDF02:02
kem_mithro: something like top_post_synthesis.blif, top_post_synthesis.v, top_post_synthesis.sdf02:02
mithrokem_: It kind of looks like it would be trivial to support arbitrary black boxes?02:02
kem_mithro: it wouldn't be too hard02:03
mithroYou already seem to have "            return std::make_shared<BlackBoxInst>(type_name, inst_name, params, input_port_conns, output_port_conns, timing_arcs, ports_tsu, ports_tcq);"02:03
kem_mithro: Yeah, there is a BlackBoxInst class but it's the code which sets up all the parameters which is type specific02:04
mithrokem_: Yeah -- it's looping over all the inputs / outputs it and setting up those structures?02:05
kem_mithro: Yep, but some of the primitives (for the verilog representation I think) also need to configure some parameters which are type specific02:06
kem_mithro: It may be possible to write generic code which uses VPR's internal data structures (e.g. t_model, from the <model> section of the architecture) to handle arbitrary simple black boxes02:07
mithrokem_: Okay02:07
kem_mithro: provided they don't have special-case behaviour02:07
mithrokem_: Well, that seemed to work...02:16
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mithrokem_: -- even passes yosys logical equivalence check! :-P02:27
kem_mithro: Nice!02:28
mithrokem_: No timing information however....02:30
kem_mithro: Yeah, I think the timing info is special case stuff in the current code.02:31
mithrokem_: Ahh - yosys doesn't like your vtr_flow/primitives.v file02:32
kem_mithro: At the time I re-wrote the netlist writer code we didn't have the timing arcs specified in the <models>, so I think its hard coded. It could likely be generalized now that we do require it to be specified.02:33
kem_mithro: The primitives.v has some funky stuff like specify blocks in there for SDF back annotation...02:33
mithrokem_: Yeah02:34
mithrokem_: Hrm, it doesn't like the top_post_synthesis.v02:41
kem_mithro: Last time I tried it, it worked with Modelsim02:46
kem_mithro: I'm off, have a good night!02:47
mithrokem_: The .blif seems to work...02:47
mithrokem_: You too!02:47
mithrokem_: Ahh the verilog code isn't connecting the clocks to the SB_DFF objects...02:48
mithrokem_: Well, the verilog is logically equivalent in some cases it seems...03:33
mithrokem_: and the blif seems logically equivalent all the time....03:34
daveshahmithro: still around?06:25
daveshahThe reason for the blif/eblif difference is you go through abc again before making the eblif06:27
daveshahBased on the synth script in the tests ice40 Makefile06:28
mithrodaveshah: yeah, I figured that one out18:34
mithrodaveshah: I'm very confused why the blif version passes logical equivalence but verilog doesn't19:27
daveshahmithro: load the blif into yosys, run write_verilog and compare19:28
mithrodaveshah: it's weird that the circuit fails check when I use SB_LUT4 provided by yosys and post pnr verilog output -- but it works when I use SB_LUT4 provided by yosys and post pnr blif output19:45
daveshahmithro: you should be able to follow the outputs backwards until you see a difference19:46
daveshahThe yosys show command might help, but I think write_verilog will be best19:46
mithrodaveshah: but it appears the SB_LUT4 provided by yosys with post pnr verilog output doesn't work at all19:47
daveshahPost an example?19:47
mithrodaveshah: but if I use the unlut version it works19:47
daveshahProbably passing parameters wrong19:47
mithrodaveshah: Yeah - that is what I think19:48
daveshahmithro: what does your verilog look like? In top_post_synthesis.v I'm seeing LUT_K not SB_LUT419:50
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daveshahmithro: .LUT_INIT(0111111110000000) is the base10 integer 0111111110000000 I think :P19:51
mithrodaveshah: replace the "YOSYS_SCRIPT  ?= synth_ice40 -nocarry; ice40_opt -unlut; abc -lut 4;" line with "YOSYS_SCRIPT  ?= synth_ice40 -nocarry;" in ice40.mk19:51
daveshahshould be 16'b011111111000000019:52
mithrodaveshah: doah19:54
mithrodaveshah: Any idea how do I tell is a param coming in from the blif is a binary string?19:54
daveshahafaik it always is19:54
daveshahunless its a string19:55
mithrodaveshah: it works \o/19:56
daveshahmithro: yay!19:57
tpbTitle: Snippet | IRCCloud (at
mithrodaveshah: So - did you know how I can convert that SB_INIT parameter into something that hlc accepts?20:03
daveshahmithro: wasn't that what your icestorm pr was about?20:11
mithrodaveshah: That allows it to accept a full 16'b value20:12
daveshahmithro: surely that should be the same as the LUT_INIT value then?20:12
mithrodaveshah: yes - but I don't know how to extend it from 4'b0110 to 16'b -- do I pad with zeros at front or back or ?20:13
daveshahmithro: it's no different from any other numeric value20:13
daveshahPad at the front20:13
daveshahIn the LUT_INIT form, anyway20:14
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