Tuesday, 2018-06-05

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digshadowstill having issues00:03
digshadowi'll post00:03
digshadowmithro: QED!00:27
mithrodigshadow: YAY!00:27
digshadowtwo tests?00:27
digshadowtrying other00:27
mithroYeah iceinv and icelut00:28
digshadowsecond pased00:28
mithrodigshadow: Need to add arachne-pnr to the env it seems00:31
mithroiCE40 FPGAs have 8 global nets. Each global net can be driven directly from an IO pin.01:18
mithroI'm reading that as "Each global net can be *only* driven directly from an single IO pin"01:19
digshadowmithro: oh btw I did confirm that one of the cr2 I/Os are input only. CLK went to a dedicated clock pin, so that precluded it from being used as an output01:19
awyglemithro: it's... More complicated than that, iiuc02:13
mithroawygle: Oh?02:14
awygleThere's two gbuf primitives02:15
awygleOne sec..02:15
mithrodigshadow: This is a bit weird -- but it does look like '/' might be valid in vpr port names...02:17
awygleah yeah, SB_GB and SB_GB_IO02:17
awygleso you can drive them from either a pin or from user logic02:17
awygleand iiuc the index-to-location mapping is different between SB_GB and SB_GB_IO02:18
awyglemithro: ^02:18
mithroawygle: okay -- I'll worry about that bit later :-P02:22
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daveshahmithro: it's worse even than that05:57
mithrodaveshah: So - how do I fix that make check error?05:57
daveshahmithro: hard enable global buffer 0's padin and wire every clock to global 005:58
daveshahBut when you get to real stuff, it's a lot more icky05:58
mithrodaveshah: I think I have things working05:58
daveshahOK, just woken up and not at pc. Can you post hlc?05:59
mithroERROR: Failed to import cell $techmap\gate.$procdff$7 (type $dff) to SAT database.05:59
daveshahThat sounds like an issue in the SAT script05:59
daveshahCan you add a clk2fflogic command after prep or proc?05:59
mithrodaveshah: I don't see a prep or proc in the EQUIV_CHECK_SCRIPT ?06:00
mithroEQUIV_CHECK_SCRIPT = rename top gate; read_verilog $(SOURCE).v; rename top gold; hierarchy; proc; miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter; sat -verify-no-timeout -timeout 20 -prove trigger 0 -show-inputs -show-outputs miter06:01
daveshahAfter proc;06:01
daveshahAdd clk2fflogic;06:01
mithrodaveshah: make check passes on both iceinv and icelut06:01
daveshahSure, but they are combinational06:01
mithroOh wait - I'm just blind :-P06:01
daveshahNvm, don't think that was right06:02
mithrodaveshah: Still same error it seems...06:02
daveshahLet me get the exact script arachne uses06:03
daveshahAfter the rename command, replace everything with:  hierarchy; proc; miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter; sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 gold 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter06:06
daveshahBut it may still fail because of reset issues. I need to look at it properly06:07
mithroERROR: Failed to parse lhs set expression `gold'.06:08
mithroEQUIV_CHECK_SCRIPT = rename top gate; read_verilog $(SOURCE).v; rename top gold; hierarchy; proc; miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter; sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 gold 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter06:09
daveshahReplace `-set-at 1 gold 1` with `-set-at 1 in 1`06:10
mithroERROR: Failed to parse lhs set expression `in'.06:13
daveshahRemove the `-set-at` expression, it doesn't work how I think it does06:15
daveshahSo remove `-set-at 1 in 1`06:15
daveshahOh awesome06:16
mithroSolving problem with 222 variables and 559 clauses.. -- SAT proof finished - no model found: SUCCESS!06:16
daveshahSounds good06:16
daveshahDo you want to know how the global networks really work now?06:17
mithrodaveshah: Trying `iceblink` now06:17
mithroiceblink QED!06:17
mithroSolving problem with 2835 variables and 7540 clauses.. -- SAT proof finished - no model found: SUCCESS!06:17
mithroI'm a bit worried that you have made everything pass with QED now :-P06:18
daveshahWell, change one of the HLC lut expressions or something and see if it breaks06:18
daveshahI realise that command only checks for 5 clock cycles06:21
mithroHrm... I changed one of the LUTs and it's still QED :-/06:21
daveshahmithro: ^06:22
daveshahAdd -tempinduct to the sat command to check for all clock cycles rather than just the first 506:22
daveshahBut that may introduce other issues06:22
daveshahTesting designs with small dividers over finite clock cycles would be easiest06:22
daveshahiceblink doesn't actually do anything within just 5 clocks06:23
mithroCan we make it like 1000 cycles?06:23
daveshahGive it a go, that still won't do anything for iceblink unless you make the divider smaller06:24
mithroChange -seq 5 to -seq 1000 ?06:24
mithroSo... How do I prove if this is working :-P -- i tried changing all the LUT values and it still doing QED...06:25
mithrobtw - I've pushed all my stuff into the 4mcmaster branches06:26
daveshahMake the divider smaller!06:26
mithrolocalparam LOG2DELAY = 22; ?06:27
mithroWhat value do you recommend?06:27
daveshahTake that down to say 6 or 806:27
daveshahWith -seq 100006:27
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)06:43
daveshahmithro: No idea06:44
daveshahSounds like HLC being weird06:44
daveshahIs that your error, or rlutz's?06:44
mithroMy improvement of his error (which was just "ParseError")06:46
daveshahDo you have multiple connections to sp4_h_r_10?06:49
daveshahOr whatever its called in HLC06:49
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)06:51
mithrodaveshah: Looks like this problem06:52
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)06:53
daveshahYes, that's not allowed in the ice40 bitstream06:53
daveshahBecause they share configuration bits06:53
mithroI wonder how that needs to be represented in the rr_graph....06:54
daveshahNo idea06:55
mithrodaveshah: https://github.com/mithro/icestorm/commit/09ca75bad7fce215fa03eadf9d189359d0f14b4107:01
tpbTitle: Improve error message. · mithro/[email protected] · GitHub (at github.com)07:01
daveshahmithro: nice07:02
mithrodaveshah: https://github.com/cliffordwolf/icestorm/pull/15007:02
tpbTitle: Improve error message. by mithro · Pull Request #150 · cliffordwolf/icestorm · GitHub (at github.com)07:02
mithrodaveshah: I think if we can figure out how that should be represented in the rr_graph format, then we have working pnr?07:06
daveshahmithro: yeah, there are a few other issues that I think will come up as we go further too07:06
daveshahThe main one I see is that the ice40 has 32 local tracks07:06
daveshahThese are shared by the 32 LUT inputs, and CEN and reset if the latter two are not on global networks07:07
daveshahThat may mean vpr will incorrectly pack some complex designs so they are unroutable. It's been a scourge of arachne, despite some attempts to deal with it07:08
daveshahBut until you have promotion of reset and CEN to global networks, it will likely mean big designs like picorv32 need a few tries07:08
mithrodaveshah: I can think of two ways to solve that07:10
mithrodaveshah: If we push the local tracks back down into the tile, then the packer won't create a packing which uses too many local tracks07:11
daveshahmithro: will vpr be able to then swap then during routing? If not, you may get suboptimal routing as I don't know if all locals are equivalent07:12
daveshahThat also relies on you knowing which reset/CEN signals are global before packing07:12
mithrodaveshah: VPR also seems to have a lot of options around packing07:14
daveshahmithro: anyway, first step is to fix the rr_graph07:16
mithroWell, I think the first step is for me to go home to bed :-P07:17
daveshahYeah sure07:19
mithroI need more brain power then I have at 15 past midnight to figure out how to represent this structure....07:19
mithrodaveshah: but I think we are extremely close07:21
* mithro is walking home now07:21
daveshahmithro: sure07:21
daveshahI think a small tweak to vpr will probably be needed, but not sure07:22
mithrodaveshah: have to ask kem_ in the morning07:23
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mithrokem_: Morning - is there a way to represent "mutually exclusive" edges in the rr_graph format? IE If you turn on edge A is means you can't turn on edge B or C?13:39
kem_mithro: Seems like you guys are making progress!14:25
kem_mithro: I think you should be able to represent it as edges A/B/C connect to a singe RR graph node14:25
kem_mithro: If that node has capacity 1, then it will be congested if more than one net tries to use A/B/C14:26
kem_mithro: At which point the router will rip-up and retry to avoid congestion/overuse14:26
mithrokem_: I'm not sure that works because the issue is the "fan out" - IE we can only fan out via a single edge14:44
mithrokem_: these are also pass gates15:04
daveshahEffectively the structure we are dealing with is a bidirectional "analog" multiplexer15:05
kem_mithro/daveshah: Is there an example I can look at (e.g. in the icestorm or lattice docs)?15:08
mithrodaveshah: did you get a chance to repo my work?15:08
daveshahmithro: yeah, I had a quick poke. reducing the log2delay further and I got QED!!! and it was a valid QED as tested by deliberate breakage15:09
daveshahkem_: here is an example https://usercontent.irccloud-cdn.com/file/m1yba8YY/Screenshot%20from%202018-06-05%2017-05-37.png15:10
daveshahfrom http://www.clifford.at/icestorm/bitdocs-1k/tile_1_16.html15:10
tpbTitle: Project IceStorm iCE40 HX1K LOGIC Tile (1 16) (at www.clifford.at)15:10
daveshahin this case, any of these signals can  be connected through a transistor to sp4_h_r_1015:10
daveshahbut the config bits are shared, so only one of these connections can be made15:10
mithroThis would all be fine if it was unidir15:11
mithroBut vpr is trying to using two of these connections at the same time15:12
kem_OK I think I follow now.15:13
mithrokem_: I'm actually thinking your idea that this is the first half of a mux more probable now15:14
kem_Like you said, for unidir routing it should work.15:15
kem_For bidir, by initial thought is you could add a 'dummy' RR node with capacity one, and use it to limit the number of connections through this mux15:16
kem_But let me think some more about it and talk to folks to see if there is a better approach15:16
mithrodaveshah: you were going to give me an understanding of the global tracks - was there anything more complicated rather than just the stuff packing problem?15:17
mithrokem_: I don't see how that works? Vpr will still think it can drive multiple outputs from this dummy rr-node15:17
daveshahmithro: yes. there are limits as to what global tracks can be used for what functions15:17
daveshahall can be used for clocks. half can be used for reset/set. half can be used for cen. any 4 of 8 can be used generally inside each logic tile15:18
daveshahthe exact rules I can't remember, but are in the datasheet15:18
daveshaheven buffers can be used for set/reset, odd numbers clock enable15:19
mithrokem_: IE the problem is fan-out15:19
kem_mithro: Yeah, you are right. Let me look into it :)15:20
mithrodaveshah: I'm wondering if Yosys should have a "global promotion" type pass..15:20
daveshahmithro: Clifford spent quite a bit of time fighting the global promotion in Synplify Pro :P15:20
daveshahGlobal promotion is for PAR, not synthesis15:21
daveshahParticularly as Yosys has no support for pin constraints15:21
mithrodaveshah: the idea this is a reset signal is lost by the time it gets to pnr?15:21
daveshahIf you use the dedicated global input pins, that ties up a global but Yosys has no way of knowing which15:21
mithrodaveshah: in what way?15:21
mithrodaveshah: btw Yosys should be able to pass arbitrary attributes / parameters to vpr15:22
daveshahmithro: the problem is the lack of understanding of a physical chip in Yosys15:22
daveshahthis would cause serious problems trying to work out things like global buffer locations, global buffer capable IO15:23
daveshahanyway pnr does know it is a reset signal because it connects to loads of reset inputs15:23
daveshahthat's how arachne does it15:23
mithrodaveshah: I was looking at the global promotion code in arachne15:24
mithrodaveshah: was trying to make it use a gb_sb_io instead of a gb_sb when it promotes a global that was on the right pin15:25
mithrodaveshah: but I got stuck with an error I couldn't understand about running of the end of a vector which seemed to be because it couldn't find where to place it15:28
mithroI could use some help with that later15:29
mithroCurrently walking15:29
daveshahmithro: oh god the global promotion code15:37
daveshahI'll see if I can help you15:38
daveshahbeware the global buffer numbers are different between SB_GB and SB_GB_IO at the same location (this is what awygle mentioned earlier I think), because SiliconBlue...15:38
awygleyup that's what I was alluding to15:46
daveshahI have to say, I would love to meet up with the old SiliconBlue people and find the reason for some of the odder parts of the ice4015:50
mithrodaveshah: So this is my patch -> https://github.com/mithro/arachne-pnr/commit/57b621cf03c3d277b044c50997d9572bac4a220c (it's just a hack at the moment)15:52
tpbTitle: HACK - Using gb_sb_io rather than gb_sb · mithro/[email protected] · GitHub (at github.com)15:52
mithroIt dies at15:52
mithroarachne-pnr: src/netlist.cc:666: void Model::check(const Design*) const: Assertion `!p2->is_bidir()' failed.15:52
daveshahmithro: beware that patch will also fail if a non-global pin is used as a clock input15:52
mithrodaveshah: Yeap15:53
daveshahbut I think the problem you're having is failing to remove the original sb_io15:53
daveshahand/or have non-global stuff attached directly to package_pin15:53
mithro$2 = {<Identified> = {static id_counter = 1859, id = 1847}, m_node = 0x5555558f27a0, m_name = "PACKAGE_PIN", m_dir = Direction::INOUT, m_undriven = Value::X, m_connection = 0x5555558ec4a0}15:56
mithro$8 = {<Identified> = {static id_counter = 1859, id = 1387}, m_node = 0x55555590c5f0, m_name = "D_IN_0", m_dir = Direction::OUT, m_undriven = Value::ZERO, m_connection = 0x5555558ec4a0}15:56
mithrodaveshah: I think it needs to be connected to "GLOBAL_ROUTING" not "D_IN_0"... ?15:57
daveshahmithro: the problem is you need to remove the original SB_IO15:57
daveshahSB_GB_IO and SB_IO are mutually exclusive15:58
mithroWhere does the SB_IO come from?15:58
daveshahio insertion, in instantiate_io in io.cc15:58
daveshahI think that's called by the time global promotion starts15:58
mithrodaveshah: Yeah - looks like it...15:58
daveshahafraid I have a meeting in a minute. Might be able to help again later15:59
mithroI can't tell if port_gc is "port global connect" or "port garbage collect"....16:06
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mithrokem_: Anyone have some compelling ideas?18:32
daveshahmithro: the former, i think18:36
daveshahi think it works out what type of port a port is18:37
daveshahso maybe global class even18:37
daveshahi.e. clock, ce, reset/set or logic18:37
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mithrodaveshah: You still around at all?20:20
daveshahmithro: yep20:37
mithroCannot route from BLK_TL-PLB.lutff_4/out[0] (rr_node: 18772 type: SOURCE ptc: 39 xlow: 13 ylow: 3) to BLK_TL-RAMB.WADDR[0] (rr_node: 16262 type: SINK ptc: 45 xlow: 11 ylow: 12) to -- no possible path22:26
mithroFailed to route connection from '$0\index[9:0][8]' to 'scratchpad.0.0.0' for net 'index[0]'22:26
mithroI'm a bit confused why it is trying to route to BLK_TL-RAMB.WADDR[0] ....22:27
mithroOh -- this is using ram tiles for some reason?22:29
mithroWelp, disabling memory makes this design *huge*22:36

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