Sunday, 2018-06-03

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mithrodaveshah: Morning15:00
daveshahmithro: morning15:00
mithrodaveshah: How's things over in Austria?15:01
daveshahmithro: Things aren't going too badly15:01
daveshahDid you get a chance to work on the tile config?15:02
mithrodaveshah: I added arbitrary metadata to pb_types -- still working on getting them in the output in a nice way15:07
daveshahmithro: nice15:08
mithrodaveshah: I don't think I understand how the bits in the bitstream work for the set/reset sync/Async stuff?16:33
daveshahmithro: let me look, haven't looked at those for a while16:33
mithroBasically how they map to the SB_FF primitives...16:34
daveshahthe relevant bits are the LC_i bits IIRC16:34
daveshahsee some info here:
tpbTitle: Project IceStorm LOGIC Tile Documentation (at
mithroLC_i[18] is the Set_NoReset bit. When this bit is set then the set/reset signal will set, not reset the flip-flop.16:35
mithroLC_i[19] is the AsyncSetReset bit. When this bit is set then the set/reset signal is asynchronous to the clock.16:35
daveshahc.f. also
tpbTitle: arachne-pnr/ at master · cseed/arachne-pnr · GitHub (at
tpbTitle: arachne-pnr/ at master · cseed/arachne-pnr · GitHub (at
mithrodaveshah: thanks! That arachne code looks exactly what I was trying to understand.16:37
daveshahmithro: yep, implement the same behaviour in and you should be golden16:38
daveshahprobably worth looking at the carry stuff there too16:38
mithrodaveshah: I'm not entirely happy with it -- but I have the enable_ff / disable_ff properties coming through now18:59
daveshahmithro: great19:00
mithrodaveshah: This is what I have at the moment ->
mithrodaveshah: This seems a bit weird...19:08
tpbTitle: Snippet | IRCCloud (at
daveshahmithro: yeah19:08
daveshahnot sure what's going on19:09
daveshahcheck the blif..19:09
mithrodaveshah: .names counter[9] counter[8] counter[7] $abc$1289$n57_1 $abc$1289$n56_1 1111 119:12
daveshahhmmm, almost looks as if the output is the wrong way round19:12
daveshahit is perhaps supposed to be a 4-input AND19:12
daveshahI think that's what the BLIF is (I hate interpreting BLIF gates)19:13
mithroWould that be a 4 input NAND?19:14
daveshah16'b0000000000000001 is a 4-input NOR, surely?19:15
daveshahbut I think the BLIF is a 4-input AND, aka 16'b100000000000000019:15
daveshahyou might want to run a small test through first to check19:15
mithrodaveshah: From
tpbTitle: symbiflow-arch-defs/lut.v at 4mcmaster · mithro/symbiflow-arch-defs · GitHub (at
daveshahmithro: yeah I think the LUTs in the HLC are the wrong way round by the usual convention, that I think the Yosys verilog uses19:21
mithroWhat do you mean by "wrong way around" ?19:21
daveshahBit 15 and 0 need the be swapped, etc19:22
mithrodaveshah: Oh - the bit ordering...19:22
daveshahBut I don't know what's parsing this, AFAIK the HLC parser in master requires an expression not an integer for LUT init19:22
daveshahI think jhol added that to his fork?19:22
daveshahAnyway, best thing to try is running an inverter through to HLC and then back through icebox_vlog19:23
jholdaveshah: correct19:23
mithrojhol: So - which way around does your hlc change expect the lut vector?19:23
jholthe right way ;)19:24
mithrojhol: I'm using your code to output the LUT value :-P19:24
jhol--- it seemed to be working correctly when I last checked it-- I exported a LUT to HLC to ASC, then converted it back to HLC and the expression was correct19:25
mithrojhol: jhol/hlc-work ?19:25
jholI guess the LSB should be I[0:3] = 4'b0000, and the MSB should be 4'b111119:26
daveshahyeah, that then matches
tpbTitle: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at
mithrojhol/ daveshah: well "make check" works for iceinv :-P19:31
daveshahjhol: awesome19:31
daveshah*mithro: awesome19:31
mithroI assume that is what19:32
mithroSAT proof finished - no model found: SUCCESS!19:32
mithromeans... (with a giant QED)....19:32
daveshahsounds good19:32
daveshahpost the icebox_vlog19:32
tpbTitle: Snippet | IRCCloud (at
daveshahyep, looks good19:34
mithrodaveshah / jhol: I pushed all my changes - want to give it a go?19:35
daveshahrebuilding vpr now19:37
mithrodaveshah: You need 4mcmaster branches of vpr, symbiflow-arch-defs and icestorm19:39
daveshahno dice for me, looks like IO config is missing19:43
daveshahERROR: Found posedge/negedge event on a signal that is not 1 bit wide at /home/david/symbiflow-arch-defs/tests/ice40/iceinv/build-ice40-top-routing-virt-HX1K/example_bitstream.v:53!19:44
daveshahmithro ^19:44
mithrodaveshah: hrm -- I wonder why it worked that first time...19:47
daveshahmaybe I need to rebuild either VPR or the arch-defs, trying both19:47
mithrodaveshah: I'm getting the same here....19:47
daveshahmithro: are you outputting any IO tile config?19:48
mithrodaveshah: Appears not - I must have manually added them ...19:51
daveshahmithro: makes sense then :P19:51
mithrodaveshah: I should be though....19:51
daveshahmithro: weird19:52
mithrodaveshah: It appears I'm not dealing with the capacity="2" properly...19:52
tpbTitle: Snippet | IRCCloud (at
mithrodaveshah: make check is working now23:02

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