Friday, 2018-06-01

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mithrodigshadow: So...00:00
mithroicebox edge entry 10 4 [['B14[12]', '!B15[11]', 'B15[13]'], 'routing', 'sp4_h_r_8', 'sp4_h_l_46']00:00
mithroGot name sp4_h_r_8 => sp4_h_l_4600:00
mithroAdding routing bidir edge 240262  P(x=10, y=4):sp4_h_r_8 (24428) => P(x=10, y=4):sp4_h_l_46 (23643)00:00
mithro   [['B14[12]', '!B15[11]', 'B15[13]'], 'routing', 'sp4_h_r_8', 'sp4_h_l_46']00:00
mithro  Add edge A 24428 => 2364300:00
mithro  Add edge B 23643 => 2442800:00
mithroIf I specify that as "sp4_h_r_8 <-> sp4_h_l_46" in HLC it works -- but if I specify it as "sp4_h_l_46 <-> sp4_h_r_8" it complains :-(00:01
digshadowthats rather odd00:05
digshadowyou are sure there isn't a type on the inverse00:06
mithrochecking now00:12
digshadowtypo00:20
mithrohttps://www.irccloud.com/pastebin/8hf9olNx/00:25
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)00:25
mithrodigshadow: ^00:25
mithro  ['routing', 'sp4_h_r_8', 'sp4_h_l_46'] ['B14[12]', '!B15[11]', 'B15[13]']00:26
mithroThis is weird...00:35
mithro10routingspan4_horz_25span4_horz_100:35
mithro11routingspan4_horz_1span4_horz_2500:36
mithrobut the bit pattern is different?00:36
digshadowHMM00:41
digshadowwe ran into something similar a while back I think00:41
digshadowI remember specifically asking a question about bit encoding on routing00:42
mithrodigshadow: I'm asking on ##openfpga00:51
mithrodigshadow: I guess I'm just going to stop generating the routing buffers in the rr_graph for now...01:03
mithrodigshadow: Hrmm, that makes things unroutable.....01:05
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daveshahmithro: I'm reasonably sure you only need to enable one05:16
daveshahTo be sure you will have to find a bitstream from icecube that only has one enabled05:16
daveshahAs for routing only working one way round, that's because HLC is crap05:29
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mithrodaveshah / jhol: could I get your help with checking that?14:33
daveshahmithro: looking at what arachne does it is definitely fine just to enable one of the switches14:34
mithroI ran into that problem when adding the bidirectional support to HLC14:34
mithroWhat happens if you enable both?14:35
daveshahmithro: nothing14:35
daveshahit will still work fine14:35
daveshahcan't see any reason not to14:35
mithroYa sure? :-P14:35
mithroHow can we confirm with icecube?14:36
daveshahmithro: build loads of designs, run them through icebox/icebox_explain until you find one with only one of the switches enabled14:37
daveshahthen hypothesis proven14:37
daveshahalternative: build a design with one/both of the switches enabled and see if they work on hardware14:37
daveshahbut thinking about the hardware (just a transistor after all) think it really shouldn't matter14:37
daveshahotherwise ask lattice :P14:37
mithrodaveshah: I don't understand hardware :-P14:38
mithrodaveshah: but they sound like dangerous last words to me :-)14:38
mithrodaveshah: Okay - for now I'll just use the direction in icebox as preference...14:52
daveshahmithro: that seems sensible, and I think that's what arachne-pnr does14:53
mithrodaveshah: http://hopper.mithis.com/~tim/errors14:56
mithrodaveshah: There are a *lot* of these?14:57
daveshahmithro: interesting14:59
mithrodaveshah: and that is *just* in the tiles I'm using14:59
daveshahhttps://www.irccloud.com/pastebin/LK5FMl15/15:02
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)15:02
daveshahthis is a known working design from arachne-pnr15:02
daveshahnotice that sp4_v_b_10 sp4_v_t_47 is set but not vice versa15:02
mithrodaveshah: fair enough15:03
mithrodaveshah: https://github.com/cliffordwolf/icestorm/pull/14715:04
tpbTitle: Allow routing (bidir) entries to be looked up in either direction. by mithro · Pull Request #147 · cliffordwolf/icestorm · GitHub (at github.com)15:04
mithrodaveshah: Well - with that pull request it seems like I _could_ be generating valid routing....15:08
daveshahmithro: if you manually add in the config (trivial for a wire, just some input/output enables) to the HLC, you should be able to use icebox_vlog to verify the bitstream15:09
mithrodaveshah: So that would be "make check" ?15:09
daveshahmithro: yep15:10
daveshahthat will do the equivalence check, although you may also want to inspect the verilog output yourself15:10
daveshahif the equivalence check fails15:10
mithrodaveshah: https://paste.ubuntu.com/p/QjtwxP8F6r/15:16
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)15:16
daveshahmithro: post mwire_bitstream.v15:17
mithrodaveshah: lol - it's the help for icebox_vlog :-P15:17
daveshahmithro: as I mentioned earlier, make check needs package, device, pcf etc set up so only works for the ice40 examples15:17
mithroAhh15:18
daveshahthat is why I created iceinv (which is actually a wire at the moment)15:18
daveshahbut that wasn't routing with the pin constraints, although you may have fixed that?15:18
mithroicebox_vlog -n top -p mwire.pcf -d vq100 vtr/tests/common/2-mwire/build-ice40-top-routing-virt-HX1K/mwire_bitstream.v15:20
mithro?15:20
daveshahmithro: lgtm, but you will only get sensible results if you also gave vpr a pin constraints file15:20
daveshahicebox_vlog isn't magic and can't get pin names from the air15:21
mithrodaveshah: icebox_vlog should complain that mwire.pcf is missing...15:21
daveshahmore importantly, it should be given an asc file not a .v file15:22
mithrodaveshah: https://github.com/cliffordwolf/icestorm/issues/14815:24
daveshahmithro: it complains for me15:26
daveshahyou sure you don't have an old (i.e more than three days) version that doesn't support -d15:26
daveshahI had to add that because you are using vq100, and icebox_vlog defaulted to the tq144 with no way to change it otherwise15:26
mithrodaveshah: oh...15:27
mithroOh - the issue is that my icebox_vlog doesn't support -d <device> argument. Probably should still exit with a non-zero exit code however.15:28
mithrodaveshah: Any idea why clifford always uses getopt rather than argparse?15:31
daveshahmithro: ask him? probably because we're C++ people15:31
daveshahif you change stuff, can you add -o to icebox_vlog too?15:31
daveshahso we don't have to do the redirection stuff15:31
mithroYeah - trivial with argparse :-P15:32
mithrodaveshah: Will get back to it after getting properties working15:34
daveshahsounds sensible15:34
mithrodaveshah: have used the "iceblink40 lp1k evaluation kit" at all?16:49
daveshahmithro: no, and don't have one16:49
daveshahI would go for the icestick16:49
daveshahit's the standard demo platform16:49
mithroI have some on order16:51
daveshahmithro: you have to use the iceburn programming tool because they have an odd onboard programmer16:52
daveshahother than that they're fine16:52
daveshahbut I'd get an icestick too16:52
daveshahfor a picorv32 demo you'll need the hx8k breakout board or similar16:52
mithrodaveshah: I have a couple on order but haven't received them yet...16:56
mithrodaveshah: Oh - maybe they should turn up today...16:56
mithrodaveshah: Back to trying to get the flipflops enabled....17:16
mithrohttps://www.irccloud.com/pastebin/S5ObO4YZ/17:54
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)17:55
mithrodaveshah: ^17:55
daveshahmithro: ?17:55
mithrodaveshah: That seems to be what I'm generating at the moment...17:56
mithrodaveshah: That should be enough to do iceinv check right?17:56
daveshahmithro: I would think so17:56
mithrooh - but iceinv seems to hit an infinite loop somewhere...17:57
mithrodaveshah: I wonder if it's caused by the fact there is nothing to place....18:01
daveshahmithro: no idea18:01
mithrodaveshah: Because the io.place file places all the available logic blocks...18:01
daveshahweird18:01
mithrodaveshah: because without the place file it seems to work...18:05
mithrodaveshah: Fixed I think...18:24
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mithrodaveshah: Fix pushed into my 4mcmaster branch...18:52
mithrodaveshah: make check fails :-(18:53
mithrohttps://www.irccloud.com/pastebin/w5dvV9Ep/18:54
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)18:54
mithrodaveshah: This also doesn't look right...18:55
mithrohttps://www.irccloud.com/pastebin/g2KlpFSo/18:56
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)18:56
mithrodaveshah: Since we don't have neigh_op wires in our rr_graph?18:57
mithrohttps://www.irccloud.com/pastebin/7Jcd6CI7/18:57
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)18:57
mithrodaveshah: I feel like this is a HLC issue there?19:03
daveshahmithro: that is probably because you are missing config19:03
daveshahSo the IO clock is set to 019:04
daveshahI actually improved the error in https://github.com/daveshah1/icestorm/commit/2b96328541204799db411f012fbe50d77d306cd419:04
tpbTitle: icebox_vlog: Valid output when IO clocks stuck at 0 · daveshah1/[email protected] · GitHub (at github.com)19:04
daveshahBut not committed yet19:05
daveshahThey neigh_op wires are shown because they are permanently connected19:05
daveshahicebox_vlog shows all wires, not just the routing path19:05
mithrodaveshah: ahh19:06
daveshahThe routing is correct, it should pass once you have config19:06
mithrodaveshah: We should add rules to run arachne-pnr too19:07
daveshahmithro: yeah, could do19:08
mithroHowever I can never spell it :-P19:09
mithroarachnne-pnr takes a long time if you don't give it an input file :-P19:17
mithroWell - it doesn't like eblif either...19:19
daveshahmithro: I think arachne allows some of the eblif features19:22
daveshahFairly certain it allows both attributes and parameters19:22
mithrodaveshah: Not .conn it seems19:22
daveshahmithro: No, that probably not19:22
mithrodaveshah: Well lunch time -- but I have arachne-pnr running so I can compare easily now19:29
daveshahmithro: you should run icetime on both bitstreams too, although arachne-pnr's timing results will be unstable with any design or seed changes19:37

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