Tuesday, 2018-05-29

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mithrojhol / daveshah -> https://github.com/SymbiFlow/symbiflow-arch-defs/pull/13205:34
tpbTitle: Add methods to RoutingGraph to determine whether any sink nodes are i… by benreynwar · Pull Request #132 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)05:34
mithronope - that wasn't what I meant to link05:35
mithrojhol / daveshah: iceblink routing - https://paste.ubuntu.com/p/JVf6gv8gpv/ -- need to get the carry working05:37
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)05:37
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mithrojhol / daveshah: morning16:20
jholmithro: hi16:20
mithrojhol: Did you see the HLC routing output stuff above?16:21
jholI did - very impressive16:21
mithrojhol: I still need to get the internal tile stuff back into the output16:22
mithrojhol: I do think that hlc turned out not to be a great choice for the output format, but we now have most of a C++ library for easily generating HLC output16:24
mithrojhol: Do you understand how HLC is suppose to work?16:29
jholin what sense?16:29
jholit seems a bit ad-hoc, I didn't find any documentation about it16:29
mithrojhol: Like - I'm a bit confused why the lutff_3/in0 net is called lutff_3/in0 rather than in0 in this example;16:30
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)16:30
jholwell yes lutff_3/ is unecessary there, but...16:31
jholI think the cell wrapper there is just a abbreviation - it will try prefixing the pin names with lutff_3/ unless you explicitly specify a pin from another cell16:32
mithrojhol: I also think I had forgotten how slow writing things in C++ is :-P16:33
jholoh yes16:33
jholit's why I wanted this code moved out into a python script that operates on the .place and .route files16:34
jhol-- well one of the reasons16:34
mithrojhol: As well, the enable_dff is basically controlling the lout or dout mux (IE direct LUT output or FF output selection mux), right?16:38
jholthat's right16:38
jholbecause there is no lout/dout net/mux in icebox16:39
mithrojhol: and what does the "LC_i[8] is the CarryEnable bit. This bit must be set if the carry logic is used." do?16:39
mithrojhol: And looking at this output16:43
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)16:43
mithroThat is effectively not using the LUT, right?16:43
jholnot using the LUT - just the carry?16:44
mithrojhol: Yeah - the output is being set to a constant 0 and then is not being routed anywhere?16:44
jholyes - in_1 is one of the inputs to the SB_CARRY16:45
daveshahlooks like a carry feed in16:45
daveshaha feed through LUT16:45
daveshahthis from arachne or VPR?16:45
mithrodaveshah: arachne16:45
daveshahyep. it inserts feed through LUTs to get signals into the carry chain, because they can't be routed in directly16:45
daveshahI think this is due to the DFFE business we discussed a while ago16:46
jholmithro: I don't know *why* you can enable/disable the carry, but you can, so I guess the answer you must enable it if you want it16:46
daveshahjhol: power saving16:46
mithrodaveshah: Well that LUT is just *not* being used the output is constant and it doesn't go anywhere16:46
daveshahice40 is very power optimised16:46
daveshahmithro: sorry /s/LUT/logic cell/16:46
daveshahthe LUT is not used, but the carry part of the logic cell is needed for feed in16:47
mithroWhat happens if you don't use "enable_carry" on one of the lutff in a cell?16:48
daveshahI assume the carry chain parts don't function16:49
daveshahprobably feeding 0 out of carry_out, but I wouldn't bank on that16:49
daveshahI think it's for power saving rather than functional purposes16:49
jholdaveshaw - shame you can't power-off the LUT of the FF16:51
jhol-- though maybe that's implicit in the configuration you do to it16:51
daveshahyes, maybe how it is implemented internally means it doesn't matter16:52
daveshahit may be that enable_carry is also set to 0 to avoid feeding crud into the carry chain but keeping it at constant 0 before a carry section starts16:52
mithrolutff_4/cout -> in_316:53
mithroI can't find which bit configures that?16:54
daveshahmithro: https://github.com/cliffordwolf/icestorm/blob/cc3c1906abe64a52ffd84a31558d87de2b74bc31/icebox/iceboxdb.py#L203816:55
tpbTitle: icestorm/iceboxdb.py at cc3c1906abe64a52ffd84a31558d87de2b74bc31 · cliffordwolf/icestorm · GitHub (at github.com)16:55
mithroOh - it's part of the routing and not part of the logic tile...16:56
daveshahyeah, part of the input mux I suppose16:56
mithrobtw - we still seem to have question marks for some of the bits?16:57
daveshahthat's where icebox_html doesn't know the type17:00
daveshahnot an actual unknown bit17:00
daveshahAFAIK there is no known bitstream generated from icecube that leaves unknown bits after icebox_explain17:00
mithrodaveshah: So what are they?17:01
daveshahthey are constant zero17:01
daveshahor at least not used by icecube17:01
daveshahsorry, doesn't know the type wasn't a good explanation17:01
daveshahnot in the database would be a better description17:02
mithrodaveshah: Column 7 very much looks like a row of unused routing bits....17:03
daveshahmithro: unlikely17:04
mithrodaveshah: Other option would be some type of padding....17:04
daveshahmore likely, mostly due to physical layout or tile changes between revisions17:05
mithrodaveshah: Or maybe something to do with internal testing?17:06
daveshahalso possible17:07
mithroThat poor lonely carry_in_mux bit in column 49 too :-P17:09
daveshahhalf of the column become the column buffer bits in the 8k17:09
tpbTitle: Project IceStorm iCE40 HX8K LOGIC Tile (1 32) (at www.clifford.at)17:09
daveshahdon't know why they moved, or what the old column buffer bits become17:09
mithroI think I have a more concrete idea about what fasm should look like after doing this HLC stuff17:17
daveshahhave you seen my prototype ECP5 config language?17:17
mithroOh, it would be good if someone could help test benreynwar's routability checker code17:17
daveshahbig example attached17:18
daveshahhere's a single tile17:18
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)17:18
benreynwarmithro:  For testing I can write a slow and simple brute-force routability checker.  Then it'll be straight forward to compare the results with the more efficient but bug-prone version.17:26
benreynwarmithro:  It's also be nice to double-check whether a simple routability checker is fast enough for real routing graphs.17:27
mithrobenreynwar: well, I hope not to have to run it very frequently17:28
mithrodaveshah: R77C63 == Row 77, Column 63? - PLC2 == tile type?17:34
daveshahmithro: R77C63 is the lattice tile name (which is at minimum a position as you see), and indeed PLC2 is the type17:34
daveshahsometimes the tile name will have a prefix too17:35
mithroarc -- PIP?17:35
daveshahyes, arc is the lattice word for pip17:35
mithrodaveshah: Does ECP5 have bidir and uni dir switches like the ice40?17:36
daveshahmithro: everything is unidir in ECP517:36
daveshahall muxes17:36
mithrokem_: Where did you get to with carry stuff in again? I know you told at the last vpr meeting but I've forgotten :-P20:22
kem_mithro: Still slogging through it. Turns out the pack pattern support we had was pretty fragile and did not generalize easily to multi-fanout/tree-patterns instead of strict chains :(20:25
mithrokem_: :-/20:26
kem_mithro: The current status is that I can detect multi-fanout patterns in the architecture, and group the atoms/netlist primitives into the appropriate molecules.20:28
kem_mithro: The part that I'm still working yet is enhancing the packing algorithm itself to support placing a molecule with multi-fanout connections within a cluster.20:29
mithrokem_: I'm actually very impressed with the catch library you are using for C++ unit tests21:05
kem_mithro: I've tried a couple different frameworks on various projects, and this seems the best so far.21:14
mithrokem_: I'm obviously used to gtest/gmock21:14
kem_mithro: Makes sense.21:15
kem_mithro:  VTR doesn't really have many unit tests yet so we'll see how it goes. Most of the code was written before unit testing was really a thing.21:16
mithrokem_: Yeah :-)21:16
mithrojhol / daveshah: The -nodffe flag is to prevent yosys from generating flipflops which don't pack nicely together?21:38

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