Wednesday, 2018-05-23

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mithrobenreynwar: Poke me and I can tell you a bit more about it00:16
mithrobenreynwar: take a look here ->
tpbTitle: symbiflow-arch-defs/testarch at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
tpbTitle: symbiflow-arch-defs/Makefile.testarch at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithrobenreynwar: and
tpbTitle: symbiflow-arch-defs/ at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
benreynwarmithro: Cheers!00:37
benreynwarmithro: Haven't looked at those links yet, but if you're around I'm bug you with a few questions first.00:39
benreynwarIt looks like with segmentlist you can get a fair bit of control over where the channel wires are connecting.  Can that work as an alternative to specifying Fc  or does it still not give you total control of how all the channel wires are connected?00:44
benreynwarmithro: testarch is just what I was looking for.  Thanks!00:56
mithrobenreynwar: Were in the world are you? I'm guessing Europe?00:57
benreynwarNah, I'm in Arizona.  Where are you?  Google suggests you're an Aussie but you're up too early for that.00:58
mithrobenreynwar: I'm currently in the US but I'm still an Aussie :-P00:59
benreynwarHa!  I grew up mostly in NZ, but have been in the US for a couple of decades.00:59
benreynwarSo I'm trying to make sense of what structures can be achieved with the VTR arch file, and when it becomes necessary to write an rr_graph.01:01
mithrobenreynwar: What are you actually trying to achieve?01:02
benreynwarmithro:  At the moment I'm just trying to understand VTR.  I thought the best way to do that is to get a few minimal designs running through the VTR flow.01:03
benreynwarbenreynwar: I'd like to choose the minimal designs so that they expose what things are easy with VTR, and when it becomes necessary to use rr_graph files.01:04
benreynwarmithro: Once I've got a selection of minimal archs, I want to follow what VTR is doing when routing on them and make sure I understand what's going on.01:05
benreynwarmithro: In the long-term I'd like to experiment with EDA algorithms, in particular with elastic netlists, but that's pretty far off.01:10
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mithrojhol: ping?13:51
mithrokem_: More speling fixes :-P
tpbTitle: A bunch of small typo fixes by mithro · Pull Request #347 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
kem_mithro: Thanks!14:59
mithroGetting closer!16:27
tpbTitle: Snippet | IRCCloud (at
mithrojhol / daveshah: ^16:27
tpbTitle: Snippet | IRCCloud (at
tpbTitle: Snippet | IRCCloud (at
mithrojhol: poke?19:18
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mithrojhol: Trying to understand the output side of things....19:44
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tpbTitle: Snippet | IRCCloud (at
digshadowmithro: is that generated from vpr?20:12
digshadow(aside: we may want to put some sort of VPR header in there)20:12
digshadowso the I/O is the last bit then?20:13
digshadowsince you have CLB internals + routing20:13
mithrodigshadow: arachne-pnr produces the following20:24
tpbTitle: Snippet | IRCCloud (at
digshadowI'm just saying, it might be good to have some traceability20:54
mithrodigshadow: I was saying maybe to the "is the last bit then?"21:06
mithroWill add the vpr output bit21:06
tpbTitle: Snippet | IRCCloud (at
digshadowmithro: lgtm22:07
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