Thursday, 2018-05-17

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elmsdaveshah: question about If there is no interconnect in the pb_type (e.g. blackbox) does the model.xml need to include the models of subcomponents? It's not clear to me how port dependencies come into play such a case.17:55
daveshahelms: no, I don't think the models of subcomponents are needed if they will never be instantiated17:56
elmsso should generate an empty model.xml if blackbox is specified?17:57
daveshahelms: I think the correct output in that case would be a model.xml with only the blackbox model in it18:00
daveshahBut I can't remember whether I ever implemented that correctly18:00
elmsdaveshah: I can look at it. Do you know of an example "only the blackbox model"? Or can you let me know what entries it would include. I'm still trying to grok the xml files fully18:03
daveshahelms: I would expect the model XML for a blackbox to look a bit like this18:05
tpbTitle: Snippet | IRCCloud (at
elmsdaveshah: ok thanks. I'll look at how to do that for the dsp4818:08
mithrokem_: This was the bug I was talking about in the meeting ->
tpbTitle: Invalid RR Graph constructed when pass_gate switches used · Issue #246 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
kem_mithro: Thanks19:36
kem_mithro: For the mux modelling discussion see Section 2.3.2 of
kem_mithro: VPR models Figure 2.9 with the 'mux' switch type19:37
mithrokem_: Okay - I'll look into it19:38
mithrokem_: The way the ice40 seems to work is that you route onto "local tracks" from spans using pass gates, the local tracks can then be connected to logic pins19:39
mithrokem_: The local tracks can also be used to connect span wires into longer wires19:40
mithrokem_: I've been thinking of the local tracks as kind of like the "crossbar" that is normally at the front of the local tiles19:42
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tpbTitle: Snippet | IRCCloud (at
mithrodigshadow: ^22:40
mithrodigshadow: Looks like vpr is correct for complaining....22:40
digshadowgot it23:00
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