Thursday, 2018-05-03

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mithrojhol: Morning!17:21
mithroIt's kind of pretty! :-P17:32
mithrojhol / daveshah: ^17:33
daveshahmithro: looks awesome!17:33
daveshahyou should sell some limited edition prints17:33
jholmithro: wow - pretty"17:33
jholmithro: so you've got span4s and span12s in that image?17:35
jholand the IO spans around 2-sides?17:35
jholdo you have any span buffers there yet?17:35
daveshah mithro: spans look good from my memory of the ice40 arch at least17:35
mithrojhol: Yeah - just the wires - not buffers or anything17:35
mithroThis was me testing an alternative theory on how to generate the rr_graph17:36
jholmithro: ok. so I still need to implement the span buffers, so if you can get me an rr_graph that routes big_xor.v successfully, then I can implement those in the HLC output tomorrow17:38
jhollast chance for me to do that :)17:39
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jholmithro: if you and digshaddow don't have time to produce an rr_graph for me, can you send me the python script you used to make those images? - I can probably hack some buffers into it, so I have something to finish my HLC writer with19:52
jholmithro: ok, so my plan for tomorrow is to finish off the DFF output, and get it to the point where I can output a counter20:06
jholthis will be done with the -nocarry and -nodffe yosys flags for simplicity20:07
jholthen I'll improvise with whatever you can send me for an rr_graph20:07
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mithrojhol: my ice40-test branch20:57

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