Wednesday, 2018-05-02

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benreynwarHey mithro00:44
kem_benreynwar: Likely your best bet is to read through some of the papers published on VPR, they give context on the algorithms and 'why' behind VPR. If you need pointers as to where to start let me know.00:46
benreynwarkem_: Cheers.  I'll read the papers, and have a look through the code and then see where I'm at.00:52
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benreynwarCould someone email me a couple of VPR papers at [email protected]?  Seems that they're not open access.05:45
benreynwar"Vaughn Betz and Jonathan Rose. Vpr: a new packing, placement and routing tool for fpga research. "05:45
benreynwar"Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, and Jonathan Rose. Vpr 5.0: fpga cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling."05:45
kem_benreynwar: Most authors keep publicly available copies on their webpages. Usually a web search on the paper title will turn these up (another option is google scholar which usually aggregates these)14:57
kem_benreynwar: VPR:
kem_benreynwar: VPR 5:
jholmitho, digshadow: ok, I have a HLC output that is successfully parsed:
jholno DFF configuration, and only in-tile routing is present at the moment15:00
jholso if I can get an rr_graph, then I can add code to emit the between-tile buffers, and we have a working LUT demo!15:02
jhol- I don't know if it's the same when you import an external rr_graph file, but at the moment if I run VPR with the HX1K layout, it gobbles up a bunch of memory and gets stuck15:04
jhol- so I've mostly been testing the HLC (as far as I can) with the test4 layout15:04
benreynwarkem_: Thanks.15:12
jhol--- ok it doesn't get stuck, just takes 10-15 minutes on my laptop15:49
jholand I can encode an asc file!15:49
jholvarious little things are missing, but still it managed to encode15:50
mithrojhol: \o/15:57
jholmithro: hi16:00
mithrojhol: Do you want to send a pull request for the hlc-out changes?16:01
jholdo we have any rr_graphs that have any buffers in?16:01
jholif I could get an rr_graph, even one that is quite incorrect, that would allow me to write the HLC translation code16:01
jhol-- well, let me walk that back a little bit...16:02
jholI want to add code to emit the span <-> span switches that are attached to the edges of the various tiles16:03
jholso if I had an rr_graph that contained those, I could emit them16:03
jholmithro: here's my commits:16:05
tpbTitle: Commits · jhol/symbiflow-arch-defs · GitHub (at
tpbTitle: Commits · jhol/vtr-verilog-to-routing · GitHub (at
tpbTitle: Commits · jhol/icestorm · GitHub (at
jholget all that stuff installed, then run:16:06
jholvpr arch.merged.xml --device HX1K --timing_analysis off big_xor.eblif --gen_post_synthesis_netlist on16:06
jholthen run top.hlc > big_xor.asc16:07
jhol...then you an decode it again with icebox_asc2hlc.py16:08
jholalso you can compare the output with what you get if you do the routing with arachne-pnr16:08
jholthe VPR "--disp on" mode looks cool now with the more detailed PIOs around the outside16:09
mithroCan you send a pull request for ?16:09
tpbTitle: Commits · jhol/symbiflow-arch-defs · GitHub (at
jholdo you have a handy git filter-branch command to add the Signed-Off line?16:10
mithrojhol: I don't understand ?16:10
tpbTitle: HACK: removed sb and cb · jhol/[email protected] · GitHub (at
jholnor do I16:11
jholat the moment, VPR seems to reject the arch XML because of that16:11
jhol-- I tested it yesterday, seems unrelated to my changes16:11
jholI'm not sure if VPR or symbiflow-arch-defs master branches got broken, but I was trying not to get sidetracked to I hacked it16:12
jhol*so I hacked it16:12
kem_jhol/mithro: Likely caused by:
tpbTitle: archfpga: Validate expected child tags of · verilog-to-routing/[email protected] · GitHub (at
kem_jhol/mithro: For 'longlines' we no longer accept <sb>/<cb> tags (since they don't actually make sens)16:14
kem_jhol/mithro: The other non-longline segments should still be OK with <sb>/<cb> tags16:15
jholkem_: thanks for the info16:15
mithrojhol: You only need to remove the sb/cb tags on the longline section, right?16:15
mithrojhol: Have you tried your code with the "top routing" version?16:15
jholmithro: I have no idea about the sb/cb tags16:15
jholmithro: I havn't tried the the top-routing verstion, but it wouldn't work, because the HLC consumes the pb_type names for metadata about how to represent the output16:16
mithrojhol: Hrm? The meta data should be the same?16:17
jholright, but things like local tracks and span-wires are missing, so there wouldn't be much output16:17
jholif the rr_graph brings those things back, then it should all work16:18
mithrojhol: Just the internal to the tile routing, right?16:19
mithrojhol: Like the LUT and stuff?16:19
jholalso the local tracks16:20
jholso for example, the HLC output code takes a node like BLK_XX-local_g[0].i[0] and uses some creative transformation to write the node in HLC format16:22
jholHLC format is basically identical to the strings you see in icebox; in the HTML bit docs16:22
tpbTitle: vtr-verilog-to-routing/ice40_hlc.cpp at hlc · jhol/vtr-verilog-to-routing · GitHub (at
jholmithro: so the top routed version should work ok, but the HLC output will probably be empty because there's not many nodes for it to walk along16:24
mithrobe back in 30 - my train just arrived16:30
tpbTitle: WIP - ice40: Fabric fixes by mithro · Pull Request #108 · SymbiFlow/symbiflow-arch-defs · GitHub (at
jholmithro: yeah I'll be back later. going to have some dinner16:33
mithroBack now16:58
mithrojhol: Just fixing up the dummy routing to make it much quicker17:09
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jholmitheo: \o/17:25
jholmithro: so you and digshadow should be able to use my HLC code17:26
jholthe key point is that if you give VPR an rr_graph file, it shouldn't cause a regression in the HLC output17:27
jhol...and you won't get the span switches yet of course17:28
jholin the meantime, I'll be adding the missing config to the IOs and then adding supports for the DFFs17:29
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tpbTitle: Implemented PIO detail, and updated PLB structure for integration with HLC output by jhol · Pull Request #109 · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithrojhol: Great, looking now17:46
mithrojhol: Can you take a look at ?17:47
tpbTitle: WIP - ice40: Fabric fixes by mithro · Pull Request #108 · SymbiFlow/symbiflow-arch-defs · GitHub (at
jholmithro: so you're commenting out span wires, local tracks and neighborhood tracks?17:49
mithrojhol: Not the local tracks?17:49
mithrojhol: Oh - you mean at the top level?17:49
jholwell yeah - but that's a good point, the local wires are still there17:49
jholso are you just removing the links from the local wires to the fc?17:50
mithrojhol: Why did you reorder the mux here -> ?17:51
tpbTitle: Implemented PIO detail, and updated PLB structure for integration with HLC output by jhol · Pull Request #109 · SymbiFlow/symbiflow-arch-defs · GitHub (at
jholwell I rebased my branch on master, where you'd done the format tidying17:52
jholdidn't want to spend time redoing the formatting17:52
jhol-- but also that mux has a duplicated LOUT -> I[2] link17:53
jholthese muxes are now defined in plb_local17:53
mithrojhol: You should just be able to use my version of the input string there right? The only change is the output and name properties?17:58
jholyeah ok - i'll fix it18:00
mithrojhol: great! Otherwise it looks all good and I think we can merge it?18:00
mithrojhol: Then I'll rebase my fabric changes on top of yours18:01
mithrojhol: I've moved back towards having span4/span12 in the tile routing...18:28
tpbTitle: Implemented PIO detail, and updated PLB structure for integration with HLC output by jhol · Pull Request #109 · SymbiFlow/symbiflow-arch-defs · GitHub (at
jholmithro: good to have the span4/span12 in the tile routing, because as far as hlc2asc is concerned, it's part of the in-tile routing18:30
mithrojhol: What I'm getting now...
jholooh... that's gorgeous18:30
jholit will look even better with PIO internals added!18:31
mithrojhol: If your pull request doesn't break travis, then I'll merge18:34
mithroHrm, looks like I need to rebuild our precompiled conda18:39
mithrodoing now....18:39
jholmithro: here's my latest HLC output on the test4 architecture with big_xor20:17
jhol-- it now has IO configs20:17
mithrojhol: \o/20:18
jholin other words, when I get the routes implemented it should work on the real device20:18
jholand here's the branch, if you want to try it:
tpbTitle: Commits · jhol/vtr-verilog-to-routing · GitHub (at
jholanyway... that's me done for the day20:19
jhollet me know how things go at your end today20:20
mithrojhol: I'll try and test it20:20
jholtry it with big_xor - any DFFs simply get missed off20:21
jhollike I say, it's interesting to use asc2hlc to decode the output of arachne-pnr for comparison20:21

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