Monday, 2018-04-30

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mithrodigshadow: Don't forget exists...19:33
tpbTitle: VPR and iCE40 Information - Google Docs (at
tpbTitle: iCE4 - iCE40 with only 4x4 tiles - Google Drawings (at
mithrodigshadow: FYI - It might be worth looking at kmurry's comment here ->
tpbTitle: rr_graph reader: review unexpected channel direction edges · Issue #335 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
digshadowyeah saw that20:41
digshadowreminds me, also I don't think we tried empty channels yet20:41
digshadowto see if that works for aesthetic purposes. or did you say you tried that and it crashes20:42
mithrodigshadow: I thought it crashed - but worth checking...20:42
digshadowcould add a dummy unroutable channel20:46
mithrodigshadow: That is what I was thinking of trying...20:46
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digshadowmithro: fyi that performance issue I mentioned earlier, is resolved. Caused by a pin ptc brute force lookup where it should have been using the index (which you already had there)23:04
mithrodigshadow: Great!23:09
digshadowrequest for comment23:11
tpbTitle: rr_graph import: clean up pin import · Issue #104 · SymbiFlow/symbiflow-arch-defs · GitHub (at
digshadowlow priority right now though23:12
mithroI don't really understand the issue -- lets discuss it later23:13

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