Friday, 2018-04-27

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digshadowmithro: I need to change the connections, but I got a generated rr_graph to load00:45
mithrodigshadow: \o/01:21
tpbTitle: testarch: Adding a testarch with a longline in it. by mithro · Pull Request #100 · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithrodigshadow: That pull request is interesting because it has a "longline" in it which is a segment which is suppose to be connected to every tile in the device..02:46
digshadowmithro: I think the bigger question is, when you say "request review" do you want an honest review02:47
digshadowor are you using it more as an FYI02:47
mithrodigshadow: More as a "check I haven't done something really stupid" type thing :-)02:47
digshadowI'm doing a super cursory look for general feel, but I'm not checking connections02:48
digshadowmithro: I have a reasonably reduced test case for the floating rr_graph arrow thing02:56
digshadowI'll create a ticket for review02:56
digshadowactually I think I know the real issue02:57
digshadowsec let me verify...02:57
digshadowit occurs when you connect between directional tracks02:58
digshadowand you are connecting to a direction that doesn't make sense02:58
digshadowit extrapolates where to draw based on the channel direction, not where the connection actually is02:58
digshadowideally the rr_graph parser would reject an rr_graph containing these02:59
mithrodigshadow: I'm unsure what should be rejected, we might want some weird connects :-P03:09
digshadowmithro: we can discuss it on the ticket03:13
digshadowalmost have it ready03:13
tpbTitle: rr_graph reader: review unexpected channel direction edges · Issue #335 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
mithrokem_: Just rediscovered
tpbTitle: Invalid RR Graph constructed when pass_gate switches used · Issue #246 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
digshadowmithro: is it legal to swap pin sides in the rr_graph vs the source xml04:17
digshadowie the reference xml says its on the left, but I output it to the right04:17
digshadowthink not04:19
mithroNo idea?04:20
digshadowI just tried a simpler case and it gave a message04:20
digshadowdraw_pin_to_chan_edge: Assertion  'grid_type->pinloc[grid_tile.width_offset][grid_tile.height_offset][pin_rr.side()][pin_rr.pin_num()]'  failed (Pin coordinates should match block type pin locations).04:20
digshadowthe other error I'm getting is more obscure, but I think its related04:21
digshadowmithro: this means that add_pins_for_block() is context sensitive to the original layout04:21
mithrodigshadow: I'm not sure I understand?05:41
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mithrohey jhol - how do things go?15:00
jholthings going alright - working on HLC15:02
mithrojhol: How is it going, I had a quick look at your changes and they looked pretty sensible as far as I could tell15:02
jholcool cool15:02
jholcan't get much further with the routing without the rr_graph, though the output isn't too far off the mark, and I think the machinery isn't too bad15:02
jholso I'm just putting in the LUT truth tables15:03
mithrojhol: So, we should be able to generate a design which is just a single PLB?15:33
mithro(and use icestorm for the fabric routing?)15:34
mithrojhol: BTW If you don't say my nick, then it is likely I'll miss you saying things here...15:35
jholmithro: yeah - we're getting there, but there's no span wires until I can run VPR with the rr_graph15:46
jholalso the PIO needs some basic implementation in the arch XML - this will be needed for the place-and-route, and the HLC converter will use the existing machinery to write out the PIO config15:48
jholalso I havn't handled the DFFs yet15:48
jholso there's a bunch of things to take care of before the output is working15:48
jholif you squint a bit, it's beginning to resemble the target:
mithrojhol: I started a PIO implementation...16:31
mithroI wonder what happened to it...16:31
digshadowmithro: btw not sure if I mentioned17:09
digshadowwhere things stand right now is that I can add IPIN/SINk type nodes17:10
digshadowbut when I add an OPIN/SOURCE VPR crashes17:10
digshadowthought I had it handy...17:11
digshadowjhol: noted you are getting near blocked, hmm17:18
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jholmithro: you did have a PIO tile that got deleted in the great rework of a couple of weeks ago18:12
jholI'll dig it back up18:12
jholmithor: I'm going to focus on the PIO, because I think if I can get an rr_graph, then with these two things and everything I have, we're close to being able to do a LUT demo18:13
jholwhich is the closest thing we have to a hello world18:13
jholbeyond that, getting the DFF up and running shouldn't be so far, but at least we have something to show if we run out of time18:14
daveshahFor now when doing IO I would keep it simple and just treat them as plain inputs or outputs18:20
daveshahThe IO register and DDR can always come later - e.g. arachne-pnr still doesn't automatically pack IO registers18:20
jholsure - nothing fancy, but we do need to get the structure a bit closer - each PIO tile has 2x pads for example18:21
daveshahYeah, of course18:21
daveshahYou'll also need to deal with the naming change between IO tile nets and logic tile nets18:22
daveshahAlso beware that the span4s in IO tiles go "around the corner" if using IO close to the corner18:22
jholthat's a problem for digshadow-c :)18:23
jhol-- hopefully we can do without span-wires on PIOs for now18:23
jholhmm.. well actually I don't know18:24
jholbut hopefully there's something that will work18:24
daveshahYeah, span wires between IO aren't needed18:25
daveshahSpan wires from IO to fabric would probably be useful, but even then I think not strictly speaking needed18:25
daveshahAs you can use the neighbour connections18:25
daveshahAll the things like the corners are in icebox anyway, so just creating a routing graph from icebox should be OK18:26
jholmithro: ok... I'm out of time for today, bit the PIO is coming along. all the inner pb_types are in. bit of work to do at the tile level still20:39
jholI'm out on Monday, and half of Tuesday, but I'll be back on the project after that20:40
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digshadowjhol: FYI I was able to pnr on some small generated rr graphs23:00
digshadowworking on cleanup + scaling a bit now23:00

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