Wednesday, 2018-04-25

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mithrodigshadow: So in trying to get you an arch.xml which generates that rr_graph.xml example you had I think I ran into another bug01:07
mithrojhol: FYI ->
tpbTitle: ice40: Getting the top-routing mode working by mithro · Pull Request #95 · SymbiFlow/symbiflow-arch-defs · GitHub (at
digshadowmithro: what did you find01:24
mithrodigshadow: I got stuck at before going of and doing other things01:25
tpbTitle: No switch is specified for the ipin cblock · Issue #332 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
digshadow    <fixed_layout height="2" name="JOHN" width="3">01:26
digshadowI feel honored, a layout has been named after me!01:26
digshadowmithro: you don't have expected behavior01:27
digshadowI'm not actually clear from your description if this is expected or not01:28
digshadowyou believe you specified the switch, but it dropped it?01:28
digshadowthe bit of code you pointed to says something about multiple fanin, I don't think that will effect the tests I'm doing now01:30
mithrokem_: Have you seen ?01:36
tpbTitle: RapidWright (at
digshadowlooks like last rapidsmith update was in 201401:54
digshadowhosted on svn sourceforge I think, so not as easy to compare vs github01:54
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mithrodigshadow: Yeah14:58
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mithroMorning kem_! Thanks for the bug fixes15:07
mithrokem_: Always awesome to wake up and see things having progressed15:07
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jholkem_: I fixed those files you pointed out15:40
kem_jhol: Great! Once CI finishes I should be able to merge it.15:41
jholkem_: thanks!15:43
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mithrojhol: Morning!17:23
mithrojhol: How goes the PLB?17:26
mithrojhol: Did you see my pull request?17:27
jholhi mithro: the HLC is coming along17:51
jholI'm getting quite close to having the tiles and the internal tile routing being written out17:51
jholthen there's the LUT config and the and various other attributes to convert17:52
jholthe main issue is that I can't really do the conversion for things like the span-wire switches until the rr_graph is completed17:56
jholare you refering to this PR?:
tpbTitle: ice40: Getting the top-routing mode working by mithro · Pull Request #95 · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithrojhol: Yes17:56
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jholwhat's the reason for the unidirectional segment wires?17:57
jholalso, with your cascade test, did you see the LOUT pin routing through to the adjacent I2 properly?18:01
mithrojhol: bidir segments appear to be broken in some way ->
tpbTitle: "found non-adjacent segments" in rr_graph when using bidirectional tracks · Issue #331 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
jholmithro: have you guys though about how we're going to fudge the IO tiles?18:14
mithrojhol: Not really18:14
jholI get the feeling that I'm going to need to spend some time on a pb_type for it, unless you have a really well  thought out plan for how it can be fudged18:14
jholat the moment our arch XML claims that it has 1-pad in the tile18:15
jholjust to give a bit more detail, this is the HLC format I'm replicating: - this file contains a counter18:16
jholhere's what I have so far:
jholdoesn't look like much, but it's been quite complex to get this far18:17
jholthe plan is to get the strings from the nodes from the XML names - the BLK_BB-xxx strings can be set up to match the inputs required by icebox_hlc2asc18:17
jholthe interal routing traversal is quite close, but there are one or two known issues to iron out18:21
jholas I say, I can't do the '<->' statements for the span wires until the rr_graph is close to being usable18:21
jholas for the io_tiles, I could hard-code some text into those, but we need to work how we would like the tile to terminate in the RR graph18:21
mithrojhol: BTW Did you see the verilog output code that inside vpr?18:21
jholI know about it - didn't use it yet18:22
mithrojhol: There might be code you can steal from that for the LUT init stuff18:22
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mithrojhol: I know there is code in there for doing the LUT rotation18:22
jholfor that I was thinking of modifying hsc2asc to accept a bitmap for that field - but maybe the verilog way would be more elegant18:24
tpbTitle: vtr-verilog-to-routing/netlist_writer.cpp at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
jholnice! - thanks18:25
mithro - We can write out the truth table as either a set of minterms (where the function is true), or a set of maxterms (where the function is false). We choose the representation which produces the fewest terms (and is smallest to represent in BLIF).18:26
mithrojhol: I should have pointed you to that file earlier18:27
tpbTitle: vtr-verilog-to-routing/netlist_writer.cpp at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
mithro //Returns a LogicVec representing the LUT mask of the given LUT atom18:28
mithrojhol: When you get a moment, can you send a WIP pull request so I can take a quick look and make sure you are heading in the right direction?18:31
jholsure - I'm about to step out, but you can take a look at what I have18:33
tpbTitle: Commits · jhol/vtr-verilog-to-routing · GitHub (at
jholyou will also need this, if you want to run it:
tpbTitle: Commits · jhol/symbiflow-arch-defs · GitHub (at
jholthis is the command line I'm running:  vpr /home/joel/workspace/symbiflow-arch-defs/ice40/devices/tile-routing-virt/arch.merged.xml --device test4 --timing_analysis off big_xor.eblif --gen_post_synthesis_netlist on18:37
jholok - got to dash, but I'll check back later18:37
digshadowmithro: the test code just dumped a rebuilt rr_graph19:24
digshadowbut it needs checking and suchj19:24
digshadowstill, a good milestone19:24
mithrodigshadow: What about into / out of vpr?19:36
digshadowI'm trying that now19:37
digshadowI'm not sure if its tracking pin associations properly right now19:38
digshadowso I suspect it will fail19:38
digshadowlooks like all of that was preserved19:43
digshadowokay I'll give it a try19:43
tpbTitle: rcfiles/xmlsort at master · mithro/rcfiles · GitHub (at
mithrodigshadow: But that isn't what I was thinking of...20:46
digshadowsort sounds scary to me20:47
digshadowthere are ordering dependencies20:47
mithrodigshadow: ET.tostring(pb_type_xml, pretty_print=True).decode('utf-8') -- that what you doing?20:47
digshadowI think? actually that might not be true20:47
digshadowdecoding ascii, but same idea20:48
digshadowah wait20:49
digshadowthink I found issue20:49
mithroSee the "serialisation" section of
tpbTitle: The lxml.etree Tutorial (at
mithrodigshadow: ?20:51
tpbTitle: lxml FAQ - Frequently Asked Questions (at
mithrodigshadow: Hrm ->
tpbTitle: sphinx-contrib-mithro/ at master · mithro/sphinx-contrib-mithro · GitHub (at
digshadowmithro: second one did it, thanks!20:57
digshadowkem_: "Message: Missing required child node 'sizing' in parent node 'switch'" upon rr_graph import21:23
digshadowdoes this need to be a required attribute?21:24
digshadowlooks like I can specify 0,0 for reasonable defaults21:26
digshadowI'll open a ticket21:26
digshadowsome easy issues if someone wants to submit a patch to vpr22:00
tpbTitle: Improve rr_graph compatibility message · Issue #334 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
tpbTitle: rr_graph: switch sizing (and timing?) should be optional · Issue #333 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
mithrodigshadow: The English in is a bit hard to understand?22:53
tpbTitle: rr_graph: switch sizing (and timing?) should be optional · Issue #333 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
digshadowmithro: it ate some of the tags22:54
digshadowI'll try to fix it up soon22:54

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