Tuesday, 2018-04-24

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digshadowjhol: https://github.com/SymbiFlow/prjxray/tree/master/tools/test_data04:48
tpbTitle: prjxray/tools/test_data at master · SymbiFlow/prjxray · GitHub (at github.com)04:48
digshadowbtw has some .fasm files04:48
digshadowmithro: approved PR04:50
jholmithro, digshadow: I've decided to do the serialization with the HLC format07:45
jholhere is an example: https://paste2.org/HIy5LZaZ07:45
jholit is a human readable textual description of the tile config07:46
jholicestorm has a converter for this format: https://github.com/cliffordwolf/icestorm/blob/master/icebox/icebox_hlc2asc.py07:46
tpbTitle: icestorm/icebox_hlc2asc.py at master · cliffordwolf/icestorm · GitHub (at github.com)07:46
jholso I'm going to take mithro's fasm walker, and rewrite it to emit HLC07:47
digshadowjhol: what is HLC used by?07:50
digshadowor is that clifford format07:50
jholI don't know- i think it's a custom format for icebox07:50
jholit doesn't need to be the long term serialization format07:51
jholbut given the time constraints it seems to be sensible to do it this way, because this way I only need to write a serializer, no deserializer07:51
daveshahHLC was a GSoC project last year IIRC08:03
daveshahI don't think anyone has used it for anything practical yet08:03
daveshahIt might be the fastest way to something practical08:04
jholdaveshah: thanks08:07
digshadowjhol: if you are going for something quick, wouldn't json be quicker?08:11
digshadoweh I guess if the other end is there, maybe08:11
digshadowanyway I don't have a strong opinion08:11
digshadowroll with whatever you think is best I'd say08:12
jholyeah - that's my thought about it08:12
daveshahmy only concern with HLC would be how well tested it is08:49
daveshahthere is no HLC support for the 5k yet, but this is something I can add in the long term08:49
jholI think there's no consensus about what a proper IR should be, or even what the requirements are for one08:51
jhol-- so doing something obviously incomplete like this will prompt us to figure what a better solution will look like08:52
daveshahYes, definitely08:54
daveshahCurrently there is a spectrum of extremes08:54
jholreally you want something that can additional metadata e.g. the verilog net names08:54
daveshahThe arachne-pnr ASC format supports that08:54
jholthe problem with ASC is that it's packed up already, so you have to write a tile packer into the PnR tool08:55
daveshahUsing `.sym <icebox net number> <user_friendly name>`08:55
daveshahBut the symbol idea could be reused08:55
daveshahIn FASM etc08:55
daveshahNot using an icebox net number but a segment name, etc08:55
jholI've been trying to find any example FASM files08:56
jholdo you have any on your hard disk lying around?08:56
daveshahNever done any FASM stuff, sorry08:56
jholno worries08:56
daveshahI doubt there's more than what's in the prjxray repo really08:56
daveshahGiven it's 7-series only it's only seem limited use08:56
mithrohey jhol / daveshah13:10
mithrojhol: fine to use HLC if it makes sense13:15
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mithrokem_: Was that architecture definition useful?17:51
kem_mithro: Yes, I was able to reproduce the issue and I'm now looking at how best to fix it17:52
mithrokem_: Great!17:59
mithrojhol: Got any updates we need to merge?18:00
digshadowjhol: I thought I linked you some yesterday18:07
digshadowdid you not see those18:07
tpbTitle: prjxray/tools/test_data at master · SymbiFlow/prjxray · GitHub (at github.com)18:07
digshadowthere are .fasm files checked in there18:08
digshadowthey are basically just key value pairs18:08
digshadowone for each configurable thing in the FPGA18:08
digshadowin ASCII format18:08
digshadowthere are some tools that disassemble a bitstream if you wanted something bigger18:08
digshadowbut I think that will give you the idea18:08
jhol:) - thanks!18:29
mithrojhol: What is the best way to give your plb stuff a go?19:35
jholmithro: make ARCH=ice40 DEVICE_TYPE=tile-routing-virt DEVICE=test4 VPR_ARGS='--disp on' counter.echo19:59
jholin the tests/ directory20:00
jholbig_xor.echo will get through to the end20:00
jholwith --disp on, you'll get the GUI and you can play around with the layout at different stages through the design20:00
mithrojhol: Looking at your interconnect - you seem to have put the I[3] mux on the I[2] pin?20:10
mithroEach LUT i has four input wires lutff_i/in_0 to lutff_i/in_3. Input lutff_i/in_3 can be configured to be driven by the carry output of the previous logic cell, or by carry_in_mux in case of i=0. Input lutff_i/in_2 can be configured to be driven by the output of the previous LUT for i>0 (LUT cascade).20:13
mithrooh, I see what you have done20:15
mithrokem_: How does vtr deal with constant generators?21:08
kem_mithro: VPR can detect constant generators from LUTs21:23
kem_mithro: It can also inferr them from blackboxes in a couple cases:21:23
mithrokem_: Is there a way to "create" a constant generator?21:23
kem_mithro: A LUT with no input is the simplest way21:24
mithrokem_: Okay - just a pb_type with the .names property but no inputs?21:24
kem_mithro: Actually, a .names in the netlist which has no inputs21:25
kem_mithro: You can set the output to 1 or 0 as the single value in the truth-table21:25
mithrokem_: Oh, I meant how do I represent a "constant generator" in the vpr architecture?21:25
kem_mithro: Ah that's a different matter21:26
kem_mithro: Currently that is something we don't model21:26
kem_mithro: Although see https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/16321:26
tpbTitle: Improve support for contant generators · Issue #163 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)21:26
mithrokem_: A lot of these architectures have a "constant generator" attached to the carry chain which can create a constant zero/constant one21:26
kem_mithro: That issue outlines what needs to be done to model constants21:27
mithrokem_: An alternative to having tieable="vcc,gnd" might be just a pb_type primitive which can generate a constant signal and a mux?21:28
kem_mithro: Yes, in fact you could probably do that now, by just making a .names pb_type with no input pins21:29
kem_mithro: So only constant generators could be mapped into it21:29
mithrokem_: That is what I was about to try21:29
mithroI assume that vpr will probably complain about the fact it should be swept away?21:30
kem_mithro: Probably, but there should be options to turn the actual sweeping off21:30
kem_mithro: Another thing to watch out for is that your input netlist may need to 'explode' the constant net into unique 2-pin net with a single driver and sink (otherwise some of the carry-chains wouldn't have a dedicated constant generator to map in)21:31
mithrokem_: Okay21:32
mithrokem_: Have you seen an error like this before;21:56
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)21:56
mithrokem_: Not doing anything strange here -- the rr_graph is being generated by vpr21:57
kem_mithro: I think that means that the generated routing is disconnected (i.e. it is not possible to connect 964 to 512 in the architecture21:57
kem_mithro: If it's a VPR rr graph then that means somethings gone wrong in the router21:58
kem_mithro: Can you file a bug?21:58
mithrokem_: Yeap, it is all generated by VPR -- will check master first21:58
kem_mithro: Thanks21:59
mithrokem_: This feels a little bit familiar last time I tried to test BI_DIR stuff :-P22:00
kem_mithro: We mostly focus on single-driver routing these days, so our regression coverage of bi-dir is more limited. It's certainly possible there is a bi-dir bug not covered our regression tests.22:02
mithrokem_: Yeah22:04
kem_mithro: I expect Artix uses uni-dir, does ice40 use bi-dir?22:05
mithrokem_: It has some bi-dir tracks22:06
mithrokem_: Is it worth trying to minimize it first? Or is that error message useful enough with a reasonable complicated arch definition?22:07
kem_mithro: If it's a simple netlist then it's probably OK as is22:08
mithrokem_: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/33122:16
tpbTitle: "found non-adjacent segments" in rr_graph when using bidirectional tracks · Issue #331 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)22:16
mithrokem_: Damn users huh? Always finding bugs :-P22:17
kem_mithro: More like helpful testers :)22:17
digshadowmithro: FYI I've rebased my stuff to master22:23
mithrodigshadow: Is it worth opening a pull request so I can start looking at it?22:26
digshadowmithro: I suppose as WIP22:27
digshadowsince things aren't fully working yet22:28
digshadowalthough I tend to push to branches a lot22:28
digshadowwhich will give you a bunch of e-mails...22:29
mithrodigshadow: Don't worry about me getting too many emails :-)22:29
digshadowalso I think I've gained a level of git mastery from working that out22:31
digshadowas a small note, I dumped any changes related to ice4022:32
digshadowmithro: opened22:45
tpbTitle: WIP rr graph lib by mcmasterg · Pull Request #94 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)22:46

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