Sunday, 2018-04-22

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kem_mithro: Yes, I believe it means complex block 2 (since I think that warning is issued after packing)01:15
kem_mithro: Also, I think that warning is a false positive for output blocks (it's warning that they have no connected outputs, which is true for an output pad)01:17
mithrokem_: so it seems that there is issues when you have muxes on the carry chain01:21
mithrokem_: the packer will select the carry input for a signal and then complain it can't route onto that signal when doing routing01:22
mithrokem_: I assume we have to do something to tell vpr to only use the carry chain inputs for carry logic?01:23
kem_mithro: for the false positive warning, can you file bug on it? I though I'd fixed it, or perhaps I only fixed it in my head :)01:24
mithroIt also seems that the router can rearrange inputs?01:25
kem_mithro: Which inputs? To the a clusterÉ01:25
mithroInputs to a block/tile01:26
kem_mithro: That is what the equivalent='true' attribute on a block port enables01:27
kem_mithro: Setting a port as equivalent effectively means 'there is a full crossbar behind this' so it's OK to swap inputs around01:28
kem_mithro: The carry-chain with mux is interesting. I'm not sure we've tried something like that before. Do you have an example?01:30
mithroBasically the input to the carry logic can either be the I0 pin (shared with the LUT) or the CIN pin01:32
mithrokem_: So, it can only swap inputs with a full crossbar?01:32
kem_mithro: For input swapping a full crossbar is what equivalent models -- effectively it means any input pin to this port can be moved to any other input pin (which is guaranteed by having a full cross-bar internally for all the pins in that port)01:35
kem_mithro: Of course you can model less than a full crossbar by using multiple smaller ports which are equivalent within themselves01:36
kem_mithro: This is one of those limitations which comes from the current split between the logic block rr graph, and routing rr graph.  If the router had full visibility into the logic block rr graph it can swap things around according to the rr graph connectivity01:37
kem_mithro: *could swap*01:38
mithrokem_: yeah01:38
mithrokem_: Is anyone working on something like that?01:38
kem_mithro: Not at the moment, but it is a long term goal.  Probably something worth discussing at the next VTR meeting.01:40
mithrokem_: Okay01:41
kem_mithro: For the carry chain mux, I have a suspicion what the issue is01:41
mithrokem_: Shall I log a issue about it?01:41
kem_mithro: That would be good01:41
mithrokem_: It's probably cause by the fact that the carry-chain input path is probably much lower delay...01:43
mithroOr that would be my guess....01:43
kem_mithro: I suspect its more fundamental than that01:43
mithrokem_: Okay01:43
kem_mithro: The packer currently assumes that any logic block input is reachable from the global routing network (it uses this if it needs to feedback a signal but there isn't enough internal routing).01:44
mithrokem_: How does it deal with carry's then?01:44
mithro(which are not connected to the internal routing)?01:45
kem_mithro: I think so far we've only modelled architectures which the only thing which connect to carry chain pins are carry chains (i.e. no mux on the carry chain)01:45
mithrokem_: Okay01:46
kem_mithro: Conceptually the fix is fairly straight forward. We just need to update the logic block internal routing graph to consider the Fc overrides and leave the CIN pin disconnected to the 'global routing' node.01:47
kem_mithro: If you can file a bug and testcase to reproduce, I can try to take a look next week01:48
mithrokem_: Okay will do01:49
mithrokem_: Will log both bugs shortly01:51
mithrokem_: Is there a way to get the clock to route like a normal signal?01:54
kem_mithro: Someone is look at that right now actually. It's the first step towards properly modelling the clock network.02:03
kem_mithro: We may have some progress on that for the next VTR meeting02:04
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