Friday, 2018-04-20

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jholmithro: hi09:31
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mithrojhol: morning!14:41
mithrojhol: Can you check that I merged everything correctly?14:43
jholis there anything significant you had to drop?16:23
digshadowjhol: btw I have a rough version of the rr graph library done, but it needs testing / debugging17:05
digshadow(also it needs an XML export still for misc parts)17:06
digshadowbut that part should be relatively straightforward17:06
mithromorning digshadow17:15
mithrojhol: I think the big thing I dropped was the xmlsort removal patch17:15
jholdigshadow: that's exciting18:01
jhol-- how far through are you in constructing the graph?18:02
jhollots of wires and muxes18:03
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digshadowjhol: last week I had some stuff going on and wasn't able to make as much progress as I was hoping18:36
digshadowso this week mostly focused on getting the core library up with a small hypothetical FPGA18:36
digshadowthis coming week will be ice40 stuff, but hopefully I can leverage some of the stuff mithro already has18:36

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