Wednesday, 2018-04-18

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mithrodigshadow: FYI - I added a carry chain to the testarch for you03:59
mithrohttps://github.com/mithro/symbiflow-arch-defs/commit/c0cb9f8404eeb88e99469fef384607adc73af06304:00
tpbTitle: testarch: Adding a carry chain to lutff. · mithro/[email protected] · GitHub (at github.com)04:00
digshadowmithro: thanks!04:02
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digshadowmithro: re: ticket comment, I think the idea is that he is talking about a from scratch rr_graph vs us reparsing one16:51
digshadowbut even then I'm not sure if its an issue, eh I'll look at his comments more soon16:51
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jholdigshadow, mithro: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/8918:11
tpbTitle: Various fixes to the PLB by jhol · Pull Request #89 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)18:11
jholso the PLB patches are in reasonable shape now18:11
jholI had to make some more changes to the structure of the PLB18:11
jholit turns out that VPR doesn't like the CARRYCHAIN <pack_pattern> crossing through mode tags18:12
jholso I pulled the LUT+CARRY out of the modal DFF elements18:12
jholthe packer seems to do the right thing with a chained LUT4 - see the big_xor.v test18:13
jholit also seems to do the right thing with a LUT->FF18:13
jholtesting counter.v it seems to fall over on routing SB_CARRY.O -> a LUT pin18:14
jholthere is a direct route with SB_CARRY.O -> LUT_CARRY.FCOUT -> LUT_CARRY.FCIN -> SB_LUT.I[2], but unless yosys selected I[2], VPR doesn't seem able to rearrange the LUT18:15
jholthe alternative route is via local tracks, but these are rather broken in the tile-routing PLB - lots of unconnected track warnings18:16
jholso when we get the rr_graph in, this problem should go away18:16
jholalso it goes away if you comment out the carry_out+carry_in fc_override i.e. add some wires from the carry wire to the global routing18:17
jholVERY VERY IMPORTANT: please can you accept these change into mainline, AND/OR rebase your branches on top of these patches18:18
jholI spent all of this Monday fixing the previous divergence - and I don't want that to happen again18:19
digshadowjhol: okay will make it a priority to review right now18:19
digshadowout of curiosity, what diverged18:20
jholthis time though, patches are not a work-in-progress mess, so it's a reasonable ask for you to rebase on it18:20
jholdigshadow: last time both mithro and I made major conflicting changes to the PLB XML18:20
digshadowjhol: says DCO is missing18:20
jholhopefully there won't be such problems this time18:21
digshadowcan you fix that while I review?18:21
jholwhat's DCO?18:21
jholok ok - I'll fix that18:22
digshadowdid you find info?18:22
digshadowlooks like mithro didn't sign his either18:22
jholyeah18:22
digshadowor at least all of htem18:22
digshadowoh wait those might just be merges18:23
jholhmm18:23
digshadowno there are unsigned18:23
jholmaybe time to use git filter-branch18:23
digshadowjhol: maybe start by signing yours and we can get mithro to fix his18:23
digshadowanyway it can't get merged into mainline until that is fixed for both you and mithro18:23
jholwell I'm not so bothered about mainline, so long as it gets rebased off of for the coming the days18:27
digshadowjhol: also looks like travis is failing18:29
digshadowdid you look into that?18:29
digshadowjhol: I'd like to get the signoff in there at least if I rebase18:29
digshadowalthough it sounds like you are conflicting more with mithro than me anyway18:30
mithrojhol: Yes, lets get your and my changes to the ice40 merged18:30
jholok... I'm rather out of time for today, so I can work on the DCO, and any other problems on Moday18:34
jholfor now, like I say it's more about divergence18:34
jholmithro: this is annoying18:36
mithrojhol: Which is annoying?18:36
jholthe solution to my SB_CARRY -> SB_LUT4 routing issue might be related to the "class" of the SB_LUT4 pb_type18:36
jholhttps://github.com/jhol/symbiflow-arch-defs/blob/modes-fixes3/ice40/primitives/sb_lut/sb_lut.pb_type.xml18:36
tpbTitle: symbiflow-arch-defs/sb_lut.pb_type.xml at modes-fixes3 · jhol/symbiflow-arch-defs · GitHub (at github.com)18:37
jholif SB_LUT4 could get class="lut", then presumably VPR would be able rearrange the LUT so it could be routed via FCOUT+FCIN18:37
mithrojhol: You need yosys to generate generic LUTs not SB_LUT418:38
jholoh ok - ignore me, it's already doing that :(18:39
jholso there's some other reason for why they're not getting wired up properly18:39
jholwell all the local tracks are messed up, so that's port of it18:39
mithrohttps://github.com/YosysHQ/yosys/blob/81a457c4a68937f8edb4c48ca5a5de86b5c05769/techlibs/ice40/synth_ice40.cc#L241-L24618:39
tpbTitle: yosys/synth_ice40.cc at 81a457c4a68937f8edb4c48ca5a5de86b5c05769 · YosysHQ/yosys · GitHub (at github.com)18:40
jholbut like I say, it should be possible to wire it with out locals, just using FCOUT/IN18:40
mithrojhol: Can you give me a better description of what you are seeing and what you are expecting?18:40
jholyeah my eblif doesn't have any, so I don't know18:40
jholjust quick explanation18:40
jholI've got to go...18:40
jholbasically if you run VPR on counter.v, it will fail to route - claiming it can't wire the SB_CARRY to a LUT18:41
jholthis can be "fixed" by commenting the carry_in/out fc_override18:41
jholand presumably it will be fixed by the rr_graph18:41
jholbut really neither should be necessary18:42
jholanyway got to go -- I'll check back later18:42
mithrojhol: So, go to tests directory and type "make ARCH=ice40 counter.echo" ?18:42
jholyes18:42
jholmake ARCH=ice40 DEVICE_TYPE=tile-routing-virt DEVICE=test4 VPR_ARGS='--disp on' counter.gdb18:42
mithrojhol: Great, I'll see if I can get time to see what is going on18:43
digshadow mithro: do you need any help reviewing the patch19:44
mithrodigshadow: jhol's patch?20:43
mithrodigshadow: No20:43

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