Tuesday, 2018-04-10

*** tpb has joined #vtr-dev00:00
*** digshadow has quit IRC01:27
*** digshadow has joined #vtr-dev02:10
*** digshadow has quit IRC02:30
*** digshadow has joined #vtr-dev02:44
*** digshadow has quit IRC02:52
*** digshadow has joined #vtr-dev03:41
jholdigshadow: no nothing further than that - but it does plug into the existing test-suite nicely07:17
jholso it beats icebox-rr_graph-import.py07:18
jholif you're working on routing, make sure you read these two thoroughly if you didn't already: http://www.clifford.at/icestorm/logic_tile.html , http://www.clifford.at/icestorm/io_tile.html07:20
tpbTitle: Project IceStorm LOGIC Tile Documentation (at www.clifford.at)07:20
jholalso - a little heads up that there are a few nets not mentioned in those docs, that are listed in the tile docs: http://www.clifford.at/icestorm/bitdocs-1k/tile_2_16.html07:21
tpbTitle: Project IceStorm iCE40 HX1K LOGIC Tile (2 16) (at www.clifford.at)07:21
*** digshadow-c has joined #vtr-dev07:24
digshadowjhol: further than what? I might be missing some backlog07:24
digshadowjhol: I did read over those07:25
jholcool cool07:25
digshadownot the latter though07:25
jholwell the point is that the written documentation in icestorm doesn't cover everything, there's more info in the tile docs07:25
jholit might be helpful to add details to the docs about the finer details of the routing07:26
digshadowI did a pr for some grammer fixes07:26
digshadowwe'll see if that gets merged first ;)07:26
jholnice - thanks!07:26
digshadowwhat was the message before the one direct to me?07:27
jhol"jhol: I see you added a boiler plate script in ice40/utils, did it go any further than that?"07:27
digshadowoh gotcha07:28
digshadownot too much new on my side. I think I pushed out some very small things07:28
digshadowbut really WIP07:28
digshadowmostly just reading docs and going over existing stuff with mithro07:29
jholso one nice thing is that with the new script, we're not building an rr_graph from scratch, so all the code related to <block_types> and <grid> can be scrapped07:29
jholso it's just the channels stuff: <channels>, <switches>, <segments>, and the graph stuff <rr_nodes>, <rr_edges>07:29
digshadoware you going to poke at it today07:30
jholI'm going to focus on resurrecting mithro's old fake-routed ice4007:30
digshadowI did run the tests dir today with ARCH=ice4007:31
digshadowand it did run some tests without failing for what that is worth07:31
jholyeah - well part of that is that I think it defaults to the "ice4" architecture, which looks a bit broken07:31
jholthe DEVICE=ice40-virt, DEVICE=hx0k seems to be the same idea as ice4, but less buggy07:32
jholice4 should probably be deleted, because there's no point trying to keep it in sync with ice40-virt:hx0k07:33
jhol* DEVICE=ice40-virt, DEVICE_TYPE=hx0k07:34
jholdigshadow: did you see this yet: https://knielsen.github.io/ice40_viewer/ice40_viewer.html ?07:37
tpbTitle: ICE40 layout viewer (at knielsen.github.io)07:37
digshadowI heard it exists, I haven't seen it07:37
jholyah, fun to play with to get a feel for what's there07:38
digshadowpretty cool07:38
digshadowhmm wonder if we could import this into VPR GUI07:39
jholthat would be cool07:39
jholI would say you have the harder slice of the job, but at least mithro is with you to help07:40
jholthe other piece of the puzzle I forgot to mention is that we'll need to write a converter that can take the VPR output and convert it into the input for icebox for the bitstream output07:41
jholthat's a task for whoever gets there first :)07:41
digshadowyes, less worried about that07:41
digshadowI'm presumably that will be relatively straightforward, but we'll see07:41
digshadowhave people showing up early tomorrow morning, need to go to sleep07:43
digshadowi'll check back in the morning07:43
jholyeah no worries!07:43
jholsleep well07:43
mithroMorning everyone13:59
mithrojhol: heyo14:00
*** mithro has quit IRC14:15
*** mithro has joined #vtr-dev14:16
jholmithro hi!14:18
mithrojhol: How goes things?14:19
jholinteresting things - I've been going through your old branch, and comparing to master14:19
jholI got the old branch to route - with a few tweaks here and there14:21
jholbut interestingly, the mast branch can route with very little tweaking14:21
jholthat's it routing ff.blif14:22
mithrojhol: Well things that are being tested on Travis should be working :-P14:23
jholwell it seems to be working alright14:23
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)14:24
jholso couple of questions:14:24
jholI've been comparing the pb_type structure between mithro/master-ice40-local-route and master14:25
jholso the main difference being how the local tracks etc. are represented14:25
jholso from what you said, it will be necessary to go back to the old structure, where the local routing is done with segments14:26
mithrojhol: Yeah14:26
jhol-- except now I'm confused, because the structure in master is actually routing14:26
mithrojhol: https://github.com/mithro/symbiflow-arch-defs/blob/rr_graph_lib_new/ice40/cells/plb/plb.pb_type.xml14:28
tpbTitle: symbiflow-arch-defs/plb.pb_type.xml at rr_graph_lib_new · mithro/symbiflow-arch-defs · GitHub (at github.com)14:28
mithrojhol: Do you recall I said not to trust anything I say? :-P14:29
mithrojhol: See how that has the comment at the bottom?14:29
jholahh yes you told me about that one14:30
jholand what happens if you uncomment it? VPR crashes?14:30
mithrojhol: So at some point in the past that was a top level pb_type14:31
jholok well it looks like I need to reassess the pros and cons of the different structures, because at the moment I'm liking the master structure more, and VPR doesn't seem to mind it14:34
mithrojhol: Then I started https://github.com/mithro/symbiflow-arch-defs/blob/rr_graph_lib_new/ice40/tiles/plb/plb.pb_type.xml which pushes a lot of the routing into the tile rather then the rr_graph14:34
tpbTitle: symbiflow-arch-defs/plb.pb_type.xml at rr_graph_lib_new · mithro/symbiflow-arch-defs · GitHub (at github.com)14:34
jholreally the routing should be factored out into an include, because it's identical in the RAM tiles14:35
mithrojhol: Possibly14:35
jholeither that, or put the RAMs and the PLBs in one common <pb_type>14:36
mithrojhol: If you can get picorv32 to work, I14:37
mithrojhol: If you can get picorv32 to work, I'm not tied to an approach...14:38
jholahh true - not a fair test!14:38
jholso this leads me on to the next question: eblif14:38
jholwrite_eblif doesn't seem to be present in my master build of yosys14:39
*** kem_ has quit IRC14:39
*** kem_ has joined #vtr-dev14:39
mithrojhol: write_blif -- http://www.clifford.at/yosys/cmd_write_blif.html14:39
tpbTitle: Yosys Open SYnthesis Suite :: Command Reference :: write_blif (at www.clifford.at)14:39
mithrojhol: See the options at the end14:40
jholoh ok - looks like the makefiles need tweaking then14:41
jholok - one other question: I see both pio-tb and pio-lr hanging around, but they both got replaced by PAD14:42
jholso is there no need for different PIO types of the horizontal and vertical edges?14:43
mithrojhol: Possibly because of the different way the routing inside a PIO tile works14:43
jholexactly - so it would seem like a regression to describe the whole the whole thing with just a "PAD" tile14:44
jholagain, if you don't know off the top of your head, I'll investigate myself14:44
tpbTitle: Project IceStorm IO Tile Documentation (at www.clifford.at)14:44
jholyeah looks like they should be different14:45
mithrodaveshah: http://www.clifford.at/icestorm/ultraplus.html -- do you have a "tile map" for the ultraplus? Like the one which you see http://www.clifford.at/icestorm/bitdocs-8k/ ?14:48
tpbTitle: Project IceStorm UltraPlus Features Documentation (at www.clifford.at)14:48
daveshahmithro: No, I need to create one at some point.14:48
mithrodaveshah: I'm looking at http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40Ultra14:49
tpbTitle: iCE40 Ultra / UltraLite / UltraPlus - Lattice Semiconductor (at www.latticesemi.com)14:49
daveshahOfficial tile map: https://user-images.githubusercontent.com/52649/27361488-845fe5fc-55dc-11e7-8a24-c2d2299d6eef.png14:49
daveshahThe routing inside the DSP and IP connect tiles are the same as in a logic tile AFAICS14:49
daveshahThose tiles are the tiles at the side (DSPs are 4 tiles)14:50
mithrodaveshah: There seems to be a 5k LUT part which doesn't have a part number? :-P14:50
daveshahIs that not the ultraplus14:51
daveshahOh, I know that table14:51
daveshahIt's borked and offset by one14:51
mithrojhol: Well do reach out if you get any further15:23
jholgoing to try picorv32 and see how that pans out15:27
*** digshadow has quit IRC15:41
mithrojhol: Great! We should make sure it is eventually done in a way that we can continually test it as part of the repo -- but for now I just want to see what happens :-)15:43
*** digshadow has joined #vtr-dev15:44
jholmaster-ice40-local-remote doesn't seem able to route led.v16:01
jhollots of errors - got to dig into what's going wrong16:02
mithrojhol: Great!16:38
jholdigshadow: just starting a 1h30 stint to finish off the day19:02
jholall going well with your stuff?19:02
digshadowjhol: taking care of some other stuff right now, but I should get back to it soon19:05
jholno worries!19:05

Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!