Friday, 2018-03-30

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tpbTitle: Post-Implementation Timing Simulation Verilog-to-Routing 8.0.0-dev documentation (at
digshadowtiming sim demo is in modelsim, wonder why that was chosen over something FOSS like iverilog / gtkwave21:57
digshadowdaveshah: have you ever tried SDF in iverilog? looks like it supports it22:02
digshadowSounds like maybe I should try to target .sdf out from the prjxray timing analysis22:02
daveshahNo, I haven't used SDF for anything other than reverse engineering ice40 timings22:03
daveshahIt has worked well for that though22:03
mithrodigshadow: No idea - kem_ can probably answer about modelsim - I'm guessing probably speed or compatibility with some type of models?22:13
digshadowdaveshah: I was looking at hte ice40 stuff. it looks like its sdf like but not quite as its missing ()22:29
digshadowmithro: the example has logic types in the testbench. I'll see if I can get it to run with iverilog22:30
daveshahdigshadow: from memory that's Clifford's intermediate format, what you get raw out of icecube is proper SDF22:31
digshadowdaveshah: okay thanks I'll take a look22:34
digshadowalso FYI I found a small error in the tutorial, making a PR22:34

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