Thursday, 2018-03-22

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mithroWhat does Warning 2: Logic block #2 (di) has only 1 input pin 'di.I[0]' -- the whole block is hanging logic that should be swept. - mean?00:51
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kem_mithro: It means VPR thinks that, since the block has no output, might be 'useless' logic (which has no effect since it doesn't fan-out anywhere) and could be removed13:32
mithrokem_: Morning15:24
kem_mithro: Hey!15:25
mithrokem_: FYI - The reason I moved to tiles with just an input and output was because I was trying to track down this rr_node without any edges issue15:26
kem_mithro: Sure, you were just the first person to give that a try which found another bug (now fixed)15:27
mithrokem_: As the rr_node without any edges seemed associated with the input/output blocks15:28
mithromy curent theory is that somewhere is treating IO block specially and doing something weird15:28
kem_mithro: That was historically the case, so it seems very plausible to me15:29
mithrobut again I haven't really had the time I would like to dig into the issue15:29
kem_mithro: Is this related to ?15:30
tpbTitle: Long tall FPGA seems to have issues causing unconnected routing · Issue #277 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
mithrokem_: Unsure - but I would like to get that one fixed too :-P15:30
kem_mithro: Its on the list, but I'm not sure when I'll get to it :)15:31
mithrokem_: I've got some one block wide and one block tall test cases that I would like to submit sometime soon15:31
mithroToday I have to work on a presentation for however15:32
tpbTitle: HDDG 28: Optics and FPGAs | Hardware Developers Didactic Galactic! (San Francisco, CA) | Meetup (at
kem_mithro: Also VTR meeting today as well, right?15:34
mithrokem_: Yeap!15:35
mithroIn like 1.5 hours right?15:35
kem_mithro: Yes, 1pm Eastern is what I have down15:40
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