Friday, 2018-03-09

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mithrokem_: VPR wouldn't really be suitable for doing PnR for "sum of products" style devices (rather than LUT style), right?19:03
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kem_mithro: VPR isn't strictly tied to LUTs as the logic implementation22:41
kem_mithro: For SoP devices (e.g. PLAs) it really depends on whether you actually need PnR to optimize something, and where you draw the line between logic synthesis and PnR22:43
kem_mithro: You could theoretically have logic synthesis spit out a netlist of ANDs/ORs and nets connecting them. If you then described the architecture (e.g. placement sites, routing graph) then VPR could theoretically then be used to do PnR22:45
kem_mithro: My experience with such devices is very limited, so I'm not sure a full-blown PnR is really necessary (e.g. is there something to optimize post-synthesis or is everything already fully determined)22:48
kem_mithro: By the time you get to something more complex like a CPLD it probably starts to make more sense22:52
mithrokem_: It was a thought experiment about what is the simplest *real* device we could generate an actual bitstream for22:53
mithrokem_: Do you have any contact with ?23:18
tpbTitle: Donnelly Centre for Cellular and Biomolecular Research (at
mithrokem_: Pondering using their library for some rendering of interconnection stuff23:18
tpbTitle: Cytoscape.js (at

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