Tuesday, 2021-08-03

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proppyis that the right place to chat about FoMU? (or freenode?)03:23
xobs[m]Yep! Chat away.03:24
proppyI've recently being going thru the workshop and was trying to built on top of the hdl/verilog step to add color cycling03:25
proppyI have some hsv2rgb logic that I exported to verilog from some DSLX/XLS: https://github.com/google/xls/pull/46803:27
proppyand I was trying to plug the 8-bit rgb output to `SB_RGBA_DRV` is realized that the RGBPWM{1,2,3} were 1 bit ports!03:28
proppyI somehow expected them to be 8bit like the register on the wishbone bus that are featured in the rest of the workshop03:29
proppybut that seems to be driven by another IP block: `SB_LEDDA_IP`03:29
xobs[m]Yeah, that's hard ip. The reference manual for it for C code is at https://rm.fomu.im/rgb.html03:29
tpbTitle: RGB — Fomu Bootloader documentation (at rm.fomu.im)03:29
xobs[m]There's a link to a document from Lattice that describes the register interface for that hard IP.03:30
proppyyep, I looked briefly at this and it looked kind-of scary to drive those directly from verilog (I'm a total newb)03:30
proppyi.e: getting the right clock/timing for setting the CSRs for data and addr.03:31
proppyit seems that the fomu bootloader had some litex glue to expose those as CSRs over the wishbone bus https://github.com/im-tomu/foboot/blob/master/hw/rtl/sbled.py#L9303:32
proppydo you think it would make sense to import those in the litex portion of the workshop?03:32
proppyand would that allow me to more easily wire the 3x 8bit bus output from my hsv2rgb to the CSRs logic generated by litex from migen?03:33
xobs[m]Yeah. You could use the `SB_RGBA_DRV` block directly and come up with your own PWM values to adjust the brightness, or you could use the `SB_LEDDA_IP` block to handle the pulses for you. 03:34
proppyin https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/csr.py#L329https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/csr.py#L329 they mention that it can be `read and optionally written by the design`03:34
proppyyep, I've tried to do some of this here: https://gist.github.com/proppy/f2a183037a5bea3c1a62b39e2f9d3d8203:35
xobs[m]You could come up with a simple state machine that cycles through the various `LEDD_ADR` bits shown on page 42 of the PDF and copies values into the registers. Not the most efficient approach, but it'll work.03:36
proppybut since those are the very first line of verilog I'm writting, I'm not sure if I'm doing things right :P03:36
proppyit does seems to be somehow working03:36
proppyI wasn't sure which PWM frequency to use to drive `SB_RGBA_DRV` directly, so I just divided the main clock by 25603:38
xobs[m]That'll work, but it'll just be a constant colour. You want a PWM signal that's high for a certain percentage of the time.03:40
xobs[m]A PWM ought to be relatively easy to put together. Here's an example I found relatively quickly: https://www.electronicsforu.com/electronics-projects/pwm-generator-microcontroller-verilog03:41
tpbTitle: Implementation of a Simple PWM Generator Using Verilog (at www.electronicsforu.com)03:41
proppyxobs: yep, that's what I think I'm doing here: with the `clockdiv` module03:44
proppy+module clockdiv(03:44
proppy+                input wire      clki,03:44
proppy+                input wire [7:0] d,03:44
proppy+                output reg clko);03:44
proppy+   reg [31:0]               counter = 0;03:44
proppy+   wire [7:0] v = counter[15:8];03:44
proppy+   always @(posedge clki) begin03:44
proppy+      counter <= counter + 1;03:44
proppy+      if ((255 - v) <= d) clko <= 1;03:44
proppy+      else clko <= 0;03:44
proppy+   end03:44
proppyI instanciate that 3x times to get a clock out of the r, g, b 8 bit buses (output of the hsv2rgb block)03:45
xobs[m]Ah yes, `d` is your duty cycle. That should work.03:46
proppydo you think it would be a useful addition to the workshop, or would that be more useful to show how to write `SB_LEDDA_IP` with litex?03:48
proppyor both? :P03:49
xobs[m]I think it could be a useful addition. It demonstrates how PWMs work, and is a good visual.03:49
proppyI'd like to consolidate those findings somewhere in case someone else try to do the same thing!03:49
proppyotherwise people new to FPGA (like me) might get under the impression that only the  risc-v part of the workshop can do color cycling easily :)03:51
xobs[m]Nice to hear you got it working!03:53
proppyI'm also curious if you have some hints/tips around verification / simulation03:54
proppyI was always trying things on the fomu directly as I was debugging this (just like the workshop show it w/ `make load`)03:55
proppybefore finding out that just calling `iverilog` like a linter (w/o even running it) can catch a lot of simple errors.03:56
proppyIs there a way to get the get yosys to be more `-pedantic`?03:57
proppyalso I realize those are kind-of fpga101 question rather than really specific to FoMu, so let me know if there is a better #chan for that :P04:05
xobs[m]Simulators are definitely your friend.04:06
proppy(although it would be cool if the workshop itself was talking a little bit about simulation!)04:06
xobs[m]I do think the workshop should mention simulation more.04:06
xobs[m]I think `gtkwave` is included in the eda tools now.04:06
xobs[m]It's the closest you can come to attaching a debugger to hardware.04:07
proppyah yes, when I tried it with the hsv2rgb stuff in, it generated a 2 GB file !04:07
proppyI also noticied that gtkwave could allow to dive down and inspect signal without other modules04:11
proppyI kinda wish there was the same thing with `$monitor` and `iverilog`.04:11
proppyfiled https://github.com/im-tomu/fomu-workshop/issues/524 and https://github.com/im-tomu/fomu-workshop/issues/525 04:23
proppyand https://github.com/im-tomu/fomu-workshop/issues/526 :)04:32
proppyxobs[m]: thanks for the chat !04:32
xobs[m]Thanks for the feedback and for using it! 04:33
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