Friday, 2019-12-06

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whatnickdaveshah: Please see this diamond error -> , any guidance is appreciated.08:00
daveshahNever seen this one before08:00
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whatnickOkay ... I also have strange behaviour from the RAM in the OrangeCrab .. other than it being a hardware error I have no clues. I am going to see if I can line up for it to be made at MacroFab and how crazy expensive that might be.11:49
daveshahWhat was the log output? Have you tried a bitstream that you know works for Greg?11:58
daveshahI know the ecp5ddrphy isn't perfect. It has only been seriously tested on the Versa11:59
whatnickYep I tried a bitstream he sent it has RAM read errors where alternative bytes are correct11:59
whatnickSee this :
daveshahIt looks more like something marginal relating to latencies in the controller or similar12:00
whatnickCool so salvageable ... ideas on fixing in gateware ?12:09
daveshahPerhaps try poking some of the magic numbers12:31
daveshahor looking at the signals with litescope (better talk to florent about that one)12:32
whatnickMagic numbers where exactly ?12:39
whatnickI am trying to see if I can get another board made. But it will be expensive without Greg's help :D12:42
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whatnickdaveshah: Pointers on magic numbers to poke ?13:22
whatnickDelays in sdram code ?13:22
daveshahI think greg pointed to a latency issue?13:23
whatnickYes ... there is a note I don't quite understand with switches between wishbone bus and soc mode13:28
whatnick#self.comb += dqs_read.eq(rddata_ens[cl_sys_latency+0] | rddata_ens[cl_sys_latency+1]) # Works only with wishbone-bridge test13:28
whatnickSo latencies differ in different modes, currently it is in SoC mode and erroring out ..13:29
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whatnickOkay I am off for tonight daveshah , will follow up on litescope suggestions. Will be fun to learn anyway.14:29
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