Saturday, 2019-10-19

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xobsmithro: it depends on the latency of gpio outputs, and how they're wired up.00:41
xobsBut potentially, yes.00:41
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mithroxobs: I have no idea what the difference between M0 / M4 is except that M4 has more "grunt" :-P02:31
xobsmithro: big difference is M0 is dumber and therefore more predictable in terms of cycle-counting.02:42
mithroYeah -- the M4 pipeline could mean you can't turn around the IO fast enough?02:58
xobsCould be, or it could be that there's a synchronizer in front of the GPIO block.  Grainuum takes advantage of the fact that on lots of M0+ chips, the GPIO is hooked up to the single-cycle port on the M0, so you get immediate, guaranteed latency.02:59
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MadHackerGrainuum is 12Mbit USB, not 1.5Mbit, yeah?08:12
xobsIt's 1.5 MB LS.08:14
MadHackerAh right.08:15
MadHackerSorry, was confused on that point. The speed requirement seemed relatively high for 1.5, but I guess there's a lot going on there.08:15
xobsFS may be possible in 80 MHz, especially with an M4, but then you start having to do things with the framing.  LS only has 8-byte packets, for example, so you don't have to oversample.08:16
MadHackerI wonder if there's scope to abuse an SPI peripheral for it? Like we do for the WS2812 signalling?08:16
MadHackerWould take some of the literal bit-banging work away, but replace it by some extra shifts.08:17
MadHacker+ would remove some of the timing predictability demands.08:17
xobsInteresting approach.  Definitely doable for the Tx side.  Lining up the Rx side could be challenging, though.08:20
MadHackerMm, mostly a matter of bit-manipulation to shift things into the right position in the frame, I guess.08:21
MadHackerDid M0/M4 both drop the old single-cycle barrel shift ARM1 had?08:21
xobsYeah, that's not in Thumb2.08:24
MadHackerShame. I know why it wasn't good from an implementation point of view in silicon, but from a programmer's perspective that thing was great.08:25
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