Friday, 2019-09-20

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xobsThe UP5K is a challenging chip to work with. "Info: Max frequency for clock 'clk12_$glb_clk': 11.62 MHz (FAIL at 12.00 MHz)"08:56
MadHackerIt's weirdly touchy about exactly what's in it, though. My 6502 was running at the full 48MHz.09:39
MadHacker"My" - arlet's.09:39
MadHackerJust got to keep an eye on the combinatorial path lengths, I guess.09:39
xobsYeah.  This is me trying to cram an MMU in there.  It's the adder, plus the dcache, plus the icache, plus that finnicky MMU.09:40
xobsNot that it's easy to see what the critical path /is/ after it's been through `abc`.09:40
MadHackerAnd an MMU is basically hell for these things, since it's always at least in the address bus path. :/09:42
xobsYeah.  But think of the cool things we could do with it!  And I'm only ~400 kHz short.09:43
xobsTime to poke at yosys options some more.09:43
MadHackerIs the cache virtually or physically mapped?09:43
MadHackerIf it's a virtual mapping you might be able to take a one-cycle hit on access to real RAM through the MMU without slowing up the cache.09:44
xobsI'm not sure.  It's just something that's part of Vex.09:44
xobsAnd it's only the icache.  I never got the dcache working with this short pipeline.09:44
MadHackerAye, fair enough. I've not looked at the RISC-V stuff beyond the first blinkenlights; I don't doubt it works, but I wanted a CPU I understood end-to-end myself.09:45
MadHacker(plus a lot of slack space in the FPGA!)09:45
xobs6502 satisfies that nicely.09:45
MadHackerAs you say.09:45
xobsBy the way, is there a decent C compiler for 6502?  Or is asm still the preferred method?09:46
MadHackercc65 produces something valid enough. I don't think I'd call it "decent", exactly, but for the sort of code you'd want to run on the 6502, it's OK.09:46
MadHackerI was using the assembler bit of it in my first non-USB-y blinkenlights project for the fomu to assemble my test ROM.09:47
MadHacker <-- this thing.09:47
tpbTitle: cc65 - a freeware C compiler for 6502 based systems (at
MadHackerThe list of supported platforms is basically a red herring. You can just add a linker script to suit whatever layout you like without much fuss.09:47
xobs`ERROR: Max frequency for clock 'clk12_$glb_clk': 11.88 MHz (FAIL at 12.00 MHz)` Getting closer.  Just 100 kHz away.09:49
MadHackerWhen I first looked at migen/litex and friends, I was sort of hoping to just drop the 6502 core and cc65 into litex, and make it build for the 6502 instead of RISC-V.09:49
MadHackerThere's quite a high bar in terms of assumptions about address bus width, space, etc. though.09:49
xobsThat should be possible.  So long as you can hook the 6502 up to Wishbone.09:50
MadHackerNot saying it's not possible, but I don't feel it's a good fit unfortunately. Shame, I'd have liked a 6502 litex.09:50
xobsI'd love to see what it would take to adapt litex to work with a 16-bit bus.09:50
xobsI think that would make the ICE40 happier.09:50
MadHackerWell, I've got that, but it's a non-transparent bus bridge, so you can't sensibly take the existing C driver code etc. and use it.09:50
xobsAnd suss out lots of bugs.09:50
xobsHow do you mean?09:51
MadHackerBasically four byte-wide registers to write an address, and then you read/write from another group of four to trigger a wishbone read/write. The first byte on a read, and the last byte on a write, triggers the wishbone transaction.09:51
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MadHackerSo the wishbone bus is basically not in the 6502's address space; just eight registers to talk to it are.09:51
MadHackerI could do a slightly fancier mapping where, say, 256 byte of 6502 address space are mapped across instead, I guess.09:52
xobsYou could adapt it to a 16-bit bus.  Or even an 8-bit bus.  Wishbone is designed to be variable-width.  Though I think that litex in particular assumes a 32-bit bus.09:52
MadHackerWishbone itself is perfectly OK with it.09:52
MadHacker(slow as hell compared to the 6502 native bus, but unproblematic)09:52
MadHackerLitex isn't.09:52
xobsHowever, litex makes heavy use of the CSR bus which is just another wishbone peripheral, and the CSR bus even on Fomu is 8-bits.09:53
MadHackerThink the latest in git has some extra parameters to let you specify the CSR spacing, but as standard it puts device CSRs something like 0x800 separation apart.09:53
MadHackerThat eats into your 16-bit space fast.09:53
MadHackerSince I can't use the litex C-side stuff at all either (non-transparent bridge) it didn't seem worth the effort; my stuff is migen-y but not litex-y.09:54
xobsWell -- and others might be interested in this too -- I've been on a big documentation kick lately, so I can get a better idea of how things are all laid out.09:54
MadHackerIf we can get a 6502 into litex, I'd be delighted, not least because that then opens up a bunch of options for using litex peripherals in real 6502 systems too.09:55
MadHackerBut also just for general understandability.09:55
xobsHere's the work-in-progress for register-level documentation for the new version of Foboot I'm working on:
tpbTitle: Documentation for LiteX SoC Project LiteX SoC Project documentation (at
xobsI need to figure out why my server is so protective about files -- the register maps might not have loaded, so if you don't see any register diagrams reload the page.09:57
MadHackerNeat. Are you forcing the CSR base addresses, or just relying on the default litex AutoCSR behaviour?09:57
MadHackerI have some diagrams, yep.09:57
MadHacker'tis tidy.09:57
xobsFor Fomu, I'm fixing the CSR bank offsets, so even if I remove CSRs the addresses won't change.09:58
MadHackerIs the USB stuff for your trififo thing?09:58
xobsSince this is the new Foboot SoC, yes.  That's trififo.09:58
MadHackerNice. That's a tidy interface.09:58
xobsI don't yet have module-level documentation, that'll come later.09:59
MadHackerHm, why does the USB_SETUP_CTRL need a bit for ADVANCE?09:59
xobsBut register-level documentation (down to the bit level) is super exciting to me.10:00
MadHackerCan't the read transaction advance the FIFO on its own?10:00
xobsMadHacker: CSRStatus registers have no `read` flag we can look for.10:00
MadHacker(Wishbone transaction)10:00
MadHackerHuh. That's sad. :/10:00
MadHackerGuess we want a CSRFIFO really for that.10:00
xobsYeah.  It might be a thing to add.10:00
xobsI wonder how difficult it would be to plumb that in.10:02
MadHackerStrikes me it's likely one of those simple, but hard to get right in 100% of circumstances, ones. Depends a bit if the CSR space handles bursts etc.10:03
xobsBut you can see how all registers are 8-bits.  The CSR bus ought to map nicely onto the 6502, provided we change the spacing.10:04
MadHackerSure, the actual register width is fine.10:08
MadHacker6502 RAM bus is somewhat non-wishbone-compatible would be the other issue, in terms of timing.10:09
MadHackerEvery cycle is prodcutively used on the 6502, excepting only for the middle cycle in a three-cycle read-modify-write.10:09
MadHackerMaking every transaction wait a cycle kind of destroys the performance of an already slow CPU. :/10:10
MadHackerArlet's 6502 runs one cycle ahead, so you can get away with it linked directly to block RAM, but you can't have anything latched in between.10:10
MadHackerIt's somewhat OK for IO, but I wouldn't want that for main RAM.10:12
xobsDesignate half of memory as mmio. I think most csr accesses assume single cycle.10:29
MadHackerThat's a quick route to no space for software. Using the BBC micro as an example - a 6502 machine with a *LOT* of IO - three pages of 256 bytes is the whole MMIO space.10:30
MadHackerBut nevertheless, yes, slower MMIO space is perfectly sane.10:31
MadHacker(and that specific computer did the same, in fact - 2MHz RAM/ROM, but 1MHz MMIO mostly)10:31
MadHackerClock-stretching magic.10:32
MadHackerHeh. Meanwhile, I have to explain to marketing here why a 27MB JPEG is not OK for the front page of a site. :D10:37
MadHackerShould make 'em build pages on a machine with 4M or RAM or something. :)10:38
ovfMadHacker: that'll also allow them to see the full page at once, no stupid landscape 16:9 crap.
MadHacker(I actually use two 16:9 monitors in portrait at home, albeit either size of a 21:9 monster landscape one)11:08
xobs`Info: Max frequency for clock 'clk12_$glb_clk': 12.09 MHz (PASS at 12.00 MHz) ` You know what? I'll take it.12:03
MadHackerCutting it fine.12:10
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xobsSure takes forever to route.13:41
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grenihi, who to compile yosys for Fomu?13:45
xobsI built `fomu-toolchain`, which includes yosys.13:46
greniI'm cheking this: when I use yosys from the fomu toolchain in work13:46
tpbTitle: GitHub - im-tomu/fomu-workshop: Support files for participating in a Fomu workshop (at
greniyes, but I have now upstream yosys, yosys from fomu toolchain, yosys from apio, yosys from litex-buildenv, yosys from symbiflow13:47
grenithat's thy I'm to not use the fomu toolchain and use yosys that I have already installed on my system13:49
greniwhen I run "python3 --board hacker" the build is fine, but the board is not booting13:50
greniso how can I compile the upstream yosys for fomu? what is needed?  a spacial patch or should it work out of the box?13:52
xobsWhat model Fomu do you have?13:52
xobsUpstream Yosys should work out of the box.  I don't know about the others -- I know the version from apio was missing things like dsp support, for example.13:53
greniafter executing "dfu-util -D build/gateware/top.dfu" USB device is getting disconnected and nothing happens13:54
grenino new USB device13:54
grenibut everything works fine when I use the fomu toolchain13:54
greniyosys from fomu reports " (Fomu build) " so I thought that it's a special version, patched for fomu13:56
xobsNo, the build just defines YOSYS_VER.  The build script (based on the Apio one) is at
tpbTitle: toolchain-icestorm/ at master · xobs/toolchain-icestorm · GitHub (at
greniok, I will pull all recent changes yosys, nextpnr, migen, litex and check it again, I did it a few days ago14:00
xobsThat should be fine, too.  Though some people on mac are reporting a regression in nextpnr speed.14:01
xobsNote also that we build with the heap placer, which I don't remember if that's enabled by default.14:01
greniok thanks, thanks also for fomu-workshop it's very useful, wishbone-tool does not work for me but I will compile it also and check all once more14:06
xobsThat's interesting that it didn't work with your version of yosys.14:06
xobswishbone-tool doesn't work?14:07
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greniyes, sometimes it works, but in 60-70% i'm getting USB error14:15
xobsWhat version of foboot is it running?14:17
greni"Fomu DFU Bootloader v1.7.2-3-g9013054"14:17
xobsThat's a relatively old version, which had some timing issues with USB.  Those should all be fixed as of v1.8.7, and SET_ADDRESS issues were fixed with
xobsThere's a lightly-tested updater at if you're feeling adventurous.  It does lots of checks before installing itself, and I've run it on my boards.14:23
tpbTitle: foboot/hacker-top-installable.dfu at master · im-tomu/foboot · GitHub (at
grenithanks, I will check, how can I update, dfu-util -D ...? :D  or I need a special JIG?14:29
xobsYes, dfu-util -D.  It takes a few seconds to check, then it goes all rainbowey while it updates.14:29
grenihmm have just tried it, dfu-util -D hacker-top-installable.dfu went fine, but after a power cycle I still have the old version14:31
xobsThat could mean that the image was corrupted.  Though I thought it was supposed to blink "red" when that happened.14:33
grenitried on two boards, same result, I will check on another PC, I think it was working better on USB 2.0 here I have 3.0 only14:35
xobsWhat is the result?14:35
xobsThe update takes about 30 seconds.  So after you upload, it takes about 10 seconds to check, then it starts the update.14:36
greniupdates takes someting about 30s, the led blinks red during the update14:36
greniafter 30 the led is turned off14:36
grenidfu-util -l shows nothis14:36
grenipower cycle14:36
grenidfu-util shows "Fomu DFU Bootloader v1.7.2-3-g9013054"14:37
xobsThat definitely sounds like a failure to upload.14:37
xobsWhat do you get when you run "file hacker-top-installable.dfu"?14:37
* ssb ponders updating his pvt v1.8.714:38
grenihacker-top-installable.dfu: data14:39
greni72706032af312534272cefbadb2441e6  hacker-top-installable.dfu14:39
ssb[373484.257738] usb 1-2: Product: Fomu PVT running DFU Bootloader v1.9.114:40
grenipwd : /tmp/foboot/releases/v1.9.114:40
xobsssb: Hooray!14:40
ssbxobs, and thanks again for the awesome stuff. )14:41
xobsgreni: That's supremely odd.  I'm going to guess it's getting corrupted somewhere during the upload.14:41
xobsssb: And thanks for testing it :)14:41
grenixobs: ok thanks, I will check on another PC, maybe after the update it will work also on this one14:42
grenimaybe I have no problem with yosys, but with the old bootloader version14:43
xobsThat's my suspicion.14:43
ssbbtw, is it "empty" now? What happens if I run "dfu-util -e" now?14:43
ssbokay, nothing interesting: it apparently rebooted itself and re-enumerated )14:44
xobsssb: Effectively, yes:
tpbTitle: foboot/main.c at master · im-tomu/foboot · GitHub (at
xobsThe actual updater software lives at offset 0x5a000, which gets erased after the update.14:45
ssbah, cool14:45
xobsSo if you run `dfu-util -e` it will actually reboot to the bitstream at offset 0x40000, which just so happens to be identical to the image at address 0.14:45
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grenixobs: I've just tried to do the update using different PC with USB2.0/3.0 and it didn't work, still old version:/, I think I will have to build the update JIG15:17
xobsgreni: What if you load hacker-top.bin?  Does that work temporarily?15:28
grenidfu-util -D hacker-top-installable.bin ?15:31
grenisorry, dfu-util -D hacker-top.bin, same result15:35
xobsgreni: I'd say that's actually a good sign.  It means that it's consistent.  For whatever reason the upload process isn't reliable on your version.  Updating it in a test jig would definitely fix that.15:36
grenixobs: thanks, I will to build it15:40
greniI will try.... should be doable15:40
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grenixobs: I've just built the jig and updated my board to "Fomu Hacker running DFU Bootloader v1.9.1", built the litex example using the latest upstream yosys17:30
greniand wishbone-tool works fine now17:30
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