Monday, 2019-09-02

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JoelSI finished going through the workshop. On Windows, at least, the litex documentation and/or build seems to be incomplete -- it produces a .bin file, but not a .dfu file.00:25
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xobsJoelS: that's a good point. When the workshop was first developed, we didn't ship dfu-util with the toolchain (well, we didn't _have_ a toolchain), so we couldn't guarantee `dfu-suffix` existed. But now we can!01:03
xobsThe `.bin` file should work, but we ought to be building a `.dfu` file as well.01:03
xobsJoelS: hmm... it looks like it ought to add the `.dfu` file:
tpbTitle: fomu-workshop/ at master · im-tomu/fomu-workshop · GitHub (at
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acathlaPreviously, on #tomu : <acathla> Anybody tried to make an ADC on an iCE40 using the diffential inputs?08:59
acathla<tnt> acathla: yeah.08:59
acathla<tnt> (I'm actually writing some code related to that right now :p)08:59
acathlatnt, any success?08:59
tntacathla: yeah, works fine.09:08
acathlatnt, how did you do it?09:09
acathlaI saw different techniques09:10
tntIn this case I'm timing the charge of a capacitor and compare the rising voltage against the one I'm trying to measure.09:11
tntI want to give delta sigma a shot, but didn't get around to it yet.09:11
acathlatnt, is your code online somewhere?09:12
tpbTitle: [VeriLog] /* * sense.v * * vim: ts=4 sw=4 * * Copyright (C) 2019 Sylvain Munaut (at
tntIt's really just a counter ... (well, two, because I time both charge and discharge to get two measurements).09:18
tntThe result is a time value that needs to be converted to voltage using RC formulas and also calibration factors to remove all the imprecisions.09:19
acathlatnt, thank you.09:21
acathlaI just found that :
tpbTitle: Simple Sigma-Delta ADC - Lattice Semiconductor (at
MadHackerDidn't bunnie publish some stuff on this?09:22
MadHackerI guess classic PC joyport stuff, too. :)09:24
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xobsSo a simple "dummyusb" implementation (no bridge) with a blink takes up 674 LCs.  It enumerates, but there's not much you can _do_ with it.11:41
xobsIt's a starting point, though!11:41
MadHackerxobs: I ended up going back to dummyusb, but I'm splitting it up into a front-end and a back-end, so there's a ControlEndpoint (and FifoEndpoints) that connect to the main bit of it.11:42
MadHackerThe only actual stuff that needs added is a bunch of muxes really.11:42
MadHackerCode separation's the bigger hassle.11:43
MadHacker*Almost* back to where I started. I'll try and find time this evening to finish it off.11:43
MadHackerThanks, though, dummyusb's been a lot easier to understand than the other implementations.11:43
MadHacker(also it only has deps on migen, not litex, which is a big help for me!)11:44
xobsMadHacker: I wonder if you could get away with doing something like `self.comb += [If(usb_core.endp == 1, fifo.din.eq(usb_core.data_recv_payload), fifo.we.eq(usb_core.data_recv_payload))]`11:45
xobsThen wire up `fifo.dout` and `fifo.readable` to your 6502 somewhere.11:46
MadHackerDangerously close; you'd need to sort out the acknowledgements, and I haven't figured out if dtb is per-endpoint.11:47
MadHackerBut yeah.11:47
xobsdtb is per-endpoint, yeah.11:47
xobsIt gets reset on SETUP, but you don't need to worry about that in this design.11:47
MadHackerJust pushed to show (not ready to use yet) - - L#14, I have a thing that builds muxes from a list, and L#361 I'm just wiring up each endpoint's version of the signals as appropriate.11:50
tpbTitle: 6502-on-fomu/ at master · jamesacraig/6502-on-fomu · GitHub (at
MadHackerSo the ControlEndpoint class is meant to be basically the guts of dummyusb minus the shared stuff that's across the whole device.11:50
MadHackerThat's where I'm going with it just now, anyway. I could hack it like you've suggested, but it seems nicer to try and build something a little more general, even if it's just for code readability.11:51
MadHackerHm, spotted a bug in the mux thing, doesn't remove default from the list it iterates over. Oh well.11:53
xobsI'm also not sure if this actually works in migen's syntax:
tpbTitle: 6502-on-fomu/ at master · jamesacraig/6502-on-fomu · GitHub (at
xobsBut if it generates the correct Verilog, then hooray!11:55
MadHackerWell, it's python syntax. It generates a list that looks like [endpoints[0].data_recv_put.eq(usb_core.data_recv_payload & 0==endpoint)]11:55
MadHackerI might have a missing () around the == clause, but that's about all.11:56
xobsI was thinking more about this:
MadHackerAh, I found that the other day.11:56
MadHackerI haven't checked the verilog output yet (still work to do before I can!) but if it breaks, then a quick migen.wrap() around the 0==endpoint will fix it.11:57
xobsYou're using `&` though, so maybe it's fine!11:57
MadHackerThat issue was near-ragequit-inducing.11:57
MadHackerwrap() calmed me down again. :)11:58
acathlaMadHacker, nice hack (hackDAC)!12:01
MadHackeracathla: Not mine, bunnie's!12:01
acathlaOh, the same bunnie from the bunnie & tim conference at CCC?12:02
MadHackerPresumably. There's only one notable bunnie, as far as I'm aware. :)12:05
MadHackerxobs: - looks OK, I probably need the () around the == clause, but nothing more elaborate.12:08
tpbTitle: debian Pastezone (at
MadHacker& vs and is important right enough tho.12:08
MadHackerDefinitely wrong with and.12:08
xobsHooray!  That's good to know.12:08
MadHackerThanks for spotting it, though, since the precedence was wrong anyway. :)12:11
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tpbTitle: WIP: Adding sphinx docs by mithro · Pull Request #4 · xobs/valentyusb · GitHub (at
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tpbTitle: WIP: Enable link-time-optimization on LiteX builds by mithro · Pull Request #253 · enjoy-digital/litex · GitHub (at
tpbTitle: Release Renode 1.8 · renode/renode · GitHub (at
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