Friday, 2019-07-26

*** tpb has joined #tomu00:00
*** xkapastel has quit IRC03:05
*** rohitksingh_work has joined #tomu04:22
*** rohitksingh_wor1 has joined #tomu05:03
*** rohitksingh_wor1 has quit IRC05:03
*** rohitksingh_work has quit IRC05:03
*** AmosSam_ has joined #tomu12:19
*** xkapastel has joined #tomu13:51
mithroMadHacker: How much space does the 6502 take?14:44
*** rohitksingh has joined #tomu14:46
*** emeb has joined #tomu14:49
MadHackermithro: - 907 out of 1280 LC's with a bit of ROM and RAM stuffed into the BRAM, using arachepnr.15:21
tpbTitle: debian Pastezone (at
MadHackerThat's basically just the 6502 itself, 512 bytes of RAM at 0x0000, 256 bytes of ROM at 0xFF00, and a 4-bit LED register at 0xFE60, and the decoding of those addresses.15:22
xobsMadHacker: could port basic to Fomu nicely...15:22
MadHackerxobs: Trivially!15:22
MadHackerThat's not my own 6502 core, BTW, that's the arlet one.15:22
tpbTitle: GitHub - Arlet/verilog-6502: A Verilog HDL model of the MOS 6502 CPU (at
MadHackerWorks well though, and it's completely trivial to get running.15:23
mithroWhy would you use arachnepnr?15:23
MadHackerIt was just handy. This was a build on a Pi where I just ran that and hadn't gotten around to building nextpnr yet.15:24
MadHackerMy fomu EVT order hasn't shipped yet, so the iCEblink ice40HX1K is all I had handy.15:25
MadHackerWell, outside my HX8K boards for the novena.15:25
MadHackerI wanted this on a Pi for other reasons (mechanical size stuff)15:25
MadHacker6502's the one CPU I know well enough to not need an assembler to build a boot ROM to test, and to be able to read the address+data buses directly and understand what's going on reliably.15:26
MadHacker26-bit ARM I might do OK too, I guess.15:26
MadHackerGive me a little while, I'll set up nextpnr and give it a go.15:31
mithroxobs: I thought all the EVT boards had shipped?15:42
MadHackerIt was a late order. Only placed it on the 13th.15:44
MadHackerFrom the website: Originally expected to ship on Jul 30, 201915:44
MadHackerCurrently expected to ship on Aug 02, 201915:44
*** alexhw has quit IRC15:45
ovfxobs: 6502 would fit together with usbuart, right?15:58
xobsovf: I don't have a usbuart yet, but I should be able to adapt dummyusb to present a uart to the device.15:59
MadHackerI suspect there are more compact 6502 cores out there. Dropping BCD mode would simplify things a bit, for example, and it's not heavily used.16:00
MadHackerBut it's already pretty small.16:00
*** rohitksingh has quit IRC16:04
MadHackermithro: NextPNR gives ICESTORM_LC:   879/ 128016:09
MadHacker(same logic)16:09
MadHackernextpnr not the weird capitalisation, sorry. :)16:09
xobsMadHacker: what if you add "-relut" to "synth_ice40" in yosys?16:09
*** xkapastel has quit IRC16:11
MadHackerNo changes, assuming it didn't need any further options.16:12
xobsThe options we use for Fomu are "synth_ice40  -top top -json top.json -relut -dffe_min_ce_use 4 -dsp"16:12
xobsStill, that's delightfully small.16:13
*** rohitksingh has joined #tomu16:20
MadHackerThe HX1K has no DSP slices so that bit doesn't work. The dffe_min_ce_use actually makes it slightly worse on this design.16:37
MadHacker(917 LCs)16:37
*** rohitksingh has quit IRC17:50
*** rohitksingh has joined #tomu18:01
tntSomeone had a 6502 running the commodore basic on an icebreaker.18:06
tntemeb: that was you right ?18:06
emebtnt: Xark took my 6502 design and ported it to icebreaker.18:07
tpbTitle: up5k_vga/demos at master · XarkLabs/up5k_vga · GitHub (at
tntemeb: oh yeah right, you were on a up5k but a custom board.18:08
emebtnt: correct18:09
*** rohitksingh has quit IRC18:35
*** rohitksingh has joined #tomu19:35
mithro900 LCs seems a lot for an 8bit CPU.....20:06
*** rohitksingh has quit IRC20:07
tntmithro: well it's also not a 8-bit cpu that was ever designed to map to fpga 4-lut architecture.20:11
mithrotnt: Yeah, true20:14
mithrotnt: And if you want to make your life miserable, might as well go all the way ;-)20:14
tnt:) I'm not sure if that code is also designed to emultate the 6502 accurately since  alot of 6502 sw tends to use "non-documented" features and so emulating bad opcodes and exact timings is often needed.20:15
tntI wrote a 16-bit cpu specificaly for the iCE40 and could only get it down to 600 LCs.20:15
emeband fwiw there's a 65C02 out there, derived from Arlet's. Not much bigger and the extra instructions are helpful:
tpbTitle: GitHub - hoglet67/verilog-6502: A Verilog HDL model of the MOS 6502 CPU (at
emebbut it's true - these 8-bit cores are definitely *not* tuned for FPGA implementation. Compared to stuff like picorv32 they run substantially slower.20:20
emeb(clock rates)20:21
*** andi- has quit IRC20:21
*** andi- has joined #tomu20:28
MadHackerBe interesting to play with one that is, and see if it can emulate a fatter CPU in a smaller number of gates.20:47
MadHackere.g. a bit-sliced implementation of risc-v.20:48
tntWell someone made a native bitsliced riscv :p20:52
*** xkapastel has joined #tomu21:29
mithrotnt: Any idea what resource usage boneless is at these days?21:50
tntmithro: About the same range at the latest news.21:51
*** emeb has quit IRC22:05

Generated by 2.13.1 by Marius Gedminas - find it at!