Saturday, 2019-05-25

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xobstnt: that is a very, very nicely-written article. And it's nice to have target values.  I'd like to, at the very least, replace the `epfifo` interface with something else.00:48
xobsProbably add a Wishbone interface, as well as a Fake Serial interface that doesn't require a CPU.00:49
xobsThe Fake Serial interface would let us use the debug bridge to debug hardware blocks more easily.00:50
xobsIt also would make it easier to set up a USB simulator to work with the valentyusb core.00:50
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tntxobs: yeah implementing a 'data pipe' from usb to custom logic without having a CPU would be very nice.05:24
tntxobs: I pretty much gave up on that on my side :/  My current plans to have a 'minimal' thing like that is to replace the riscv with a more minimal CPU I designed because I just have a hard time seeing how to respond to all the control request in a half-way complant way without it.05:25
xobstnt: all that it needs to do is enumerate as *something*. Which it sounds like yours does, and tinyfpga does, and a bunch more do. It's just another state machine to glom onto the lower-level SM.05:26
tntEven the original TinyFGPA boot loader (which is far from compliant) is already 1400 LCs.05:26
xobsThat one enumerates as a CDC-ACM though, right? So it has multiple endpoints to deal with.  We'd only need EP0.05:27
tntYes it does CDC-ACM. But you said above you wanted a fake serial interface ?05:28
xobsYou're right. My mistake. We just need a Fake Interface.06:52
xobsAll it needs to do is respond to the common requests (device and configuration descriptors), and that's it.06:53
xobsCould get fancier and respond to string requests.06:58
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mithroxobs: How do I build a RPi image for a production Fomu tester?23:17
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