Tuesday, 2019-05-21

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xobsmithro: did you have any?00:22
xobsMy plan is to have everything live on a FAT12 partition that starts at offset 262144 (256kB) from the SPI image.01:11
xobsIf you're booting from the DFU bootloader, it'll treat that region as raw disk and either boot that RISC-V image or warmboot the FPGA.01:12
xobsIf you're booting from the MSC bootloader, it'll ensure that it's FAT12-formatted, and then present itself as a MSC disk.  Once you eject/unmount the disk (or touch a particular file, maybe?), it'll defragment the SPI FAT partition and move /boot.X to offset 0x41000 (FAT12 sector 8).01:14
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mithroxobs: I did have some comments...01:39
mithroxobs: Is this the right document? https://docs.google.com/spreadsheets/d/1RumoVlaTyYCGBCcCKFjigD4A6gUNujb8Fpnj_O5XAS8/edit#gid=001:42
tpbTitle: Google Sheets - create and edit spreadsheets online, for free. (at docs.google.com)01:42
xobsmithro: that's the one I'm working on, yes.01:45
mithroxobs: See the write protect sheet?01:47
xobsmithro: I do, yes.01:47
mithroxobs: I think that was for the hacker fomu?01:49
xobsMy plan for protection was to do away with it for the initial release.  Basically, have the DFU "backup" bootloader not change those bits at all.01:52
xobsThe "MSC" bootloader, which is what lives at offset 0x1a000, will set those bits as appropriate prior to jumping to user code.01:52
xobsOr, alternately, it will install an update itself.01:52
xobsThe theory being that the DFU bootloader is a sort of "MVP".01:53
mithroYou didn't list your SPI flash part in your schematic for the evt board?01:54
xobsOne thing I haven't seen yet -- and maybe I should look today -- is whether it's possible to reset those bits without a power cycle.  I suspect it is, in which case maybe I'll protect the first 128k.01:55
xobsThe EVT SPI flash is a W25Q128JVSIM -- you're right, maybe I should have made that the KiCad "Value" rather than the KiCad "MPN".01:56
xobsI updated the EVT schematic with the part number.02:02
mithroxobs: For some reason I thought the Hacker Fomu had less SPI flash than the production fomu?02:06
xobsIt does -- 1 MB vs 2 MB02:06
mithroThat is what I thought, but the schematic for the hacker says I loaded the Adesto AT25SF161 ?02:10
xobsAnd that's the manual that I have in "reference", too. Well cool.02:11
mithroxobs: That makes things easier...02:12
mithroUndersell, over deliver I guess?02:13
mithroWhat are you using on the production boards?02:14
xobsThere are two options. I believe they're using GD25Q16CEIGR but MX25R1635FZUIH0 is also pin-compatible.02:15
mithroxobs: are they config options compatible?02:31
xobsmithro: a lot of the configuration options are unique per chip. We'll need to read the ID fields to figure out how to configure the parts.02:35
mithroxobs: okay02:35
mithroxobs: Do you know how much space FAT12 takes up?02:41
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xobsmithro: I have a mkfs.vfat incantation that uses 1536 bytes.02:46
xobs`dd if=/dev/zero of=dt.img bs=1024 count=128 && mkfs.vfat -R 1 -f 1 -F 12 -h 0 -r 16 dt.img && mount -oloop dt.img /mnt && perl -e 'print(chr(0x9a)) while(1)' | dd of=/mnt/file.txt bs=1 ; umount /mnt ; hexdump -C dt.img`02:47
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xobsMass production of the PCBA starts next week! https://twitter.com/tomu_im/status/113070892763558297605:45
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ssbhi! Comparison table at the main Fomu page lists "None" GPIOs.  But, if I'm reading the schematics correctly, the four input pads are connected to FPGA directly and can be configured as general I/O, right?13:51
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mithrossb: You are correct23:06
mithrossb: I believe the Fomu Production and Fomu Hacker boards are slightly different in how those pads are connected though...23:08

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