Friday, 2019-04-19

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mithrofutarisIRCcloud: I've yet to figure out if there is a good way to use cocotb with migen00:16
futarisIRCcloudmithro: Yeah, I saw you wrote about it ~3 years ago.  ...01:02
xobsfutarisIRCcloud: reading is working, and writing is working too, but the writing state machine gets into a funny position and ends up corrupting the next packet.01:48
xobsToday is a holiday, but I still want to work on this and get that fixed.01:48
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futarisIRCcloudI know that feeling... Being able to use the bridge will make the fomu a whole lot more useful.02:04
xobsHow? "ICESTORM_LC:  5232/ 5280    99%" routes and passes timing.05:04
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xobsIt works, so now I'll add bridge support to litex. That'll be the last piece before we can have debugging support with gdb.05:35
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tntxobs: I'm still not entirely clear what that bridge is or what the use is ?06:28
xobstnt: the bridge exposes the entire Wishbone bus to the host.06:30
xobsHappily, the cpu has a debug port on the Wishbone bus, so with the briidge we can hook up gdb.06:31
xobsYou can also develop drivers on your host system by doing #include "generated/csr.h" and replacing the read() and write() macros with one that does a bridge call.06:40
keesjthe tutorial here might be nice creates a SPIMaster on the wishbone . after building /flashing it is possible to write a pyhon script(uart->wishbone bridge) to implement a device specific spi protocol
tpbTitle: fpga_101/ at master · enjoy-digital/fpga_101 · GitHub (at
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tntxobs: ok, I see.08:33
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futarisIRCcloudxobs: I might just end up using it on arty with pmod-usb-raw if we run out of space.10:26
tpbTitle: prj-pmod/hardware/pmod-usb-raw at master · TomKeddie/prj-pmod · GitHub (at
tpbTitle: OSH Park ~ (at
tpbTitle: Port to Xilinx Series-7 (such as the Artix) FPGAs · Issue #2 · tinyfpga/TinyFPGA-Bootloader · GitHub (at
xobsfutarisIRCcloud: cool! always looking for more people to test.11:05
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