Thursday, 2019-04-18

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xobsThere's still some build weirdness with valentyusb.  It has about a 50% chance of not working once synthesized.  Tweaking the design fixes it.  Hmm...00:25
xobsThe interesting thing is that these builds *kinda* work, they just lock up after a few packets.  I should see if it's Wishbone locking up or something else.00:28
xobsThe good news is that the USB<->Wishbone bridge looks entirely doable, and yesterday I got "reading" working (i.e. I was able to transfer 4 bytes back to the host, but the "ADDRESS" field wasn't working right so unless I hardcoded the address they weren't the _correct_ 4 bytes.)00:47
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mithroxobs: Normally if you see that behaviour I would say that you are missing a timing constraint01:41
xobsmithro: what do you mean by timing constraint?  You mean that I have a clock network that's getting identified as the wrong frequency?02:10
mithroxobs: A clock network which is missing a timing constraint (in ISE it was common to be cause by the constraint not making it through a PLL or other similar primitive)02:11
mithroxobs: I would expose the current state of the import FSM as registers and check their values02:13
xobsWhat's the import FSM?02:19
xobsI was under the impression that it was the FSM, yeah.  I thought maybe it was getting into an "ERROR" state, but I patched it so that it immediately exits that state, but that didn't change things.02:19
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xobsmithro: according to the nextpnr output, the timing is all correct.03:26
xobsThough some of the async stuff has awfully short timings.03:26
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mithroxobs: My goal for latchup is to help you get the valentyusb hardware rock solid03:43
mithroxobs: I was also pondering seeing if we refactor valentyusb to look like the second diagram ->
tpbTitle: valentyusb - Parts - Google Drawings (at
mithroAnyway home time for me03:46
xobsmithro: that's my goal, too, since I'm planning on a trip to start production right after I get back.03:46
mithroxobs: btw you have a form2 3d printer thingy right?03:50
xobsmithro: yes, that's what I'm using to prototype the cases.03:53
mithroxobs: could you print up some of the little programmers that were recently posted to the Tomu list?04:19
mithroThat way I can give out a sheet to Fomu hacker boards with a programming jig04:20
mithroIt was designed to be printed with a form 204:20
mithroMuch more portable then the factory jig :-)04:22
xobsmithro: do you have any idea why "If((byte_counter == 1) or (byte_counter == 2) or (byte_counter == 3) or (byte_counter == 4)" gets turned into "if ((usb_byte_counter == 3'd4)) begin" in Verilog?04:26
xobsLooks like it's a bug in migen:
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xobsmithro: also, the FSM only gets into the "ERROR" state sometimes.  Not always.  I think there are two failures here.  One where the FSM goes into "ERROR", and another that I still haven't figured out.05:01
* xobs uploaded an image: image.png (598KB) < >05:03
xobsThe first one/two/three packets work successfully, but then things start to fail afte rthat.05:04
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tntxobs: (1) the fact the core doesn't use the IOB registers is often a recipe for random build results.  (2) the 'async fifo' fix I really meant as a quick hack to see if that was the issue, but depending on clock drift between host/fomu I'm pretty sure it can still go wrong some times. Ideally the architecture of the RX pipeline should be fixed.06:38
xobstnt: I'm actually starting to suspect it has to do with the phase difference between the 48 MHz and 12 MHz domains.  If I build using "--with-pll", the problem doesn't seem to happen.06:39
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xobsI'm reasonably certain the issue is caused by skew, since it goes away when I use the pll. Nextpnr doesn't support cross-domain timing constraints, so that makes sense.09:28
xobsAnyway. I have Wishbone reading working reasonably reliably now! Wishbone writing isn't quite there yet, but I just need to get the sequence right. And litex_server support is delightfully easy.09:29
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futarisIRCcloudxobs: So the bridge is semi working now?  We can read from the fomu using the bridge?23:15
futarisIRCcloud - If anyone here hasn't already seen it.   I wonder if we should start writing some testbenches for foboot and the like...23:17
tpbTitle: GitHub - potentialventures/cocotb: Coroutine Co-simulation Test Bench (at

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