Tuesday, 2019-03-26

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mithroxobs: It looks like the applet has a bunch of addresses to start from00:32
mithroxobs: https://docs.google.com/spreadsheets/d/1GpODSOEyMLW0n-oLtM2OK5VHUZfGAMkQ0Hzdnw_t2y4/edit?pli=1#gid=000:34
tpbTitle: Google Sheets - create and edit spreadsheets online, for free. (at docs.google.com)00:34
futarisIRCcloudxobs: So can I flash the hacker boards using foboot and bit-banged SPI now?00:36
xobsfutarisIRCcloud: nearly there. I have managed to erase and program exactly 256 bytes. It gets stuck after that, so today I'll try and finish it up.00:38
xobsThen I need to get rebooting working.00:38
xobsmithro: the SB_WARMBOOT block has two bits. Maybe there's a header that needs to get stuck on the front of the Foboot Bitstream.00:40
mithroxobs: That is correct00:40
mithroxobs: See the second sheet00:40
xobsDoes it scan all of spi looking for the correct image?00:45
xobsOr do these four configuration words go at the start of the first image?00:46
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mithroxobs: These go at address 000:47
xobsDoes each get a sync word?00:48
mithroxobs: As far as I can see00:49
mithroxobs: The "applet" is 128 bytes long, with 32bytes per offset thingy00:50
xobsThat clears things up a bit, thanks. I wonder why they're so large. No crc16?00:54
tpbTitle: icestorm/icemulti.cc at master · cliffordwolf/icestorm · GitHub (at github.com)00:54
xobsI see how these could interact with the FPGA Bitstream state machine.00:54
mithroxobs: I think it's because the header thingy only fits in 17 bytes, and 32 bytes is the next 2^n offset?00:57
mithroxobs: What flash device are you using?01:02
xobsmithro: there are a few, I'd need to go check. I actually need to update Foboot to work with the dvt flash.01:03
xobsI mean, it works right now as-is, but it doesn't identify the capacity correctly, and there might be some quirks.01:04
mithroxobs: I'm pondering about write protect01:10
mithroThe device can be software protected against erroneous or malicious program or erase operations by utilizing the NonVolatile Protection feature of the device. Non-Volatile Protection can be enabled or disabled by using the Write Status Register command to change the value of the Protection (CMP, SEC, TB, BP2, BP1, BP0) bits in the Status Register.01:11
mithroxobs: I'm trying to figure out what the spiflash layout should look like...01:27
mithroxobs: Interestingly, the bitstream is 102kbytes, so in a 128kbytes region you could have the FPGA+bitstream + 28kbytes of program....01:38
xobsThat was my thought.  We could actually use the bootloader CPU to run user programs.01:42
xobsMakes it easier to pass data back and forth between the bootloader and RISC-V programs, if necessary.01:42
mithroxobs: So I was thinking if you get 28kbyte of program per 128kbyte region with bitstream, if we did "failsafe bootloader + embedded foboot, bigger bootloader, riscv cpu + embedded bios" we could fit in the first 256kbyte of flash and have ~56kbytes of flash for the bigger bootloader01:57
futarisIRCcloudSounds reasonable02:00
mithroxobs: then we can write protect the first 256kbytes of the flash02:01
xobsThe two SPI flash stuff options I picked both have similar registers for that, though I'm still trying to understand how the MX25R1635FZUIH0 works.02:06
xobsThey look different, but that's fine that's just a special case for updating Foboot, and it can be worked out in a Fomu version of Booster.02:09
xobsmithro: "booster" is the program that you stick a new version of Toboot onto the end of to update Tomu.  Kinda like a booster rocket.02:11
tpbTitle: tomu-bootloader/booster at master · im-tomu/tomu-bootloader · GitHub (at github.com)02:11
mithroxobs: The question is how big a UF2 bootloader is going to be02:24
xobsmithro: that is the question.02:24
xobsI've run out of space, which makes it difficult to add debugging.02:24
xobsSo I'm getting the debugger working instead.02:25
mithroxobs: for foboot?02:25
xobsI don't think UF2 will be much larger.  I'd guess UF2 would be maybe twice as large.02:25
xobsYeah, for the DFU mode.  DFU should be the failsafe mode.02:25
mithroxobs: your running foboot inside the bitstream right?02:26
xobsYes, Foboot is within the bitstream.02:27
xobsHowever, with the full UF2 bootloader, I think it should be outside of the bitstream, which should free up enough BRAM to use epfifo with more than just the one endpoint.02:27
mithroxobs: Should also figure out how big micropython is....02:31
futarisIRCcloudYou'll need a few endpoints for USB Mass Storage, for UF2...02:32
futarisIRCcloudHas anyone hooked up a vexriscv simulator to a litex bridge?02:34
mithrofutarisIRCcloud: The renode was doing something like that02:34
xobsfutarisIRCcloud: I've done an awful lot of the reverse.02:37
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xobsWhyyyyyy.  I hook up the debugger and everything just works.02:41
mithroWhat are you trying to debug?02:44
xobsmithro: Foboot's DFU mode.  It was getting into a state where it stopped responding, and my assumption was that it was spinning waiting for SPI flash.02:45
xobsBut today it's mostly working.02:45
xobsOh well, it's nice to have a debugger at least.02:45
xobsUnfortunately I have the debugger working using the UART, which is only on EVT boards.02:47
xobsNow I'm playing the try-to-get-it-to-meet-timing game03:32
xobsIt is not a fun game.03:32
mithroxobs: Didn't you do some work on the epmem interface?03:53
xobsmithro: I did some, but I stopped work on it in favour of getting something up and running.03:54
mithroxobs: That should only increase the LC count while keeping the mem count the same03:54
xobsI have something working, and the system is validated, so now I can pick it up again.  Once I have free time, of course.03:54
mithroI had an interesting idea about how to do fast interrupts on riscv on ice4004:06
mithros/fast interrupts/fast context switches/04:07
mithroAs we use a register file, we actually have a whole bunch of spare space fo have copies of the registers04:07
xobsBanked/windowed registers?04:08
mithroso it would be pretty simple to "save" the registers by just having an offset into the register file04:08
xobsIt's an interesting idea.  And would save a lot of time for context switches.04:09
mithroxobs: It would in fact just end up being mapped to the top bits of address....04:09
mithroxobs: I was thinking that you might keep the bottom 16 constant and the top 16 are banked, as frequently you still need to access the registers which have arguments and stuff?04:10
mithroand there is already the RISC-V mode were you only have 16 registers -- embedded mode04:10
xobsYeah, embedded mode might be nice to have for performance reasons.04:11
futarisIRCcloudmithro: https://www.sifive.com/blog/all-aboard-part-7-entering-and-exiting-the-linux-kernel-on-risc-v04:11
xobsThough the banked idea does get around the issue nicely.04:11
mithroThe RISC-V calling convention passes arguments in registers when possible. Up to eight integer registers, a0–a704:14
xobsAnd that's $x10-$x1704:15
xobsLogical register $a0 is physical register $x10.  Like how logical register $zero is physical register $x0, and logical register $sp is physical register $x2.04:17
tpbTitle: riscv-calling-convention.md · GitHub (at gist.github.com)04:20
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ewenFor those playing along at home, https://github.com/im-tomu/fomu-tests/pull/6 contains my draft attempt at making the Fomu blink example buildable for Fomu Hacker boards too.  (Still works on EVT2/EVT3; builds for FOMU_REV=hacker, but I don't have a hacker board to test with).06:14
tpbTitle: WIP: Support EVT and non-EVT Fomu boards by ewenmcneill · Pull Request #6 · im-tomu/fomu-tests · GitHub (at github.com)06:14
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futarisIRCcloudCheck out @zephray_wenting’s Tweet: https://twitter.com/zephray_wenting/status/1110384453048774658?s=0907:45
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xobsthanks for the changes, ewen!09:12
xobsWow, programming is so much easier when you have a debugger.  Even better when you have *hardware breakpoints*.09:12
xobs(Which, let me tell you, makes debugging ROM code so luxurious.)09:13
ewenxobs: Debuggers and breakpoints are defintely very useful for certain types of bugs :-)09:13
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ewenxobs: Re changes, you're welcome.  I learned a bunch getting it compiling.  I'd suggest reviewing and ideally testing on a hacker board before merging.09:14
xobsI don't actually have any hacker boards wired up.  I'll do that once I get DFU working.09:15
ewenCool, thanks.  Good luck with DFU.  (I'm off to bed now, BTW.)09:19
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xobsI'm 90% of the way there with DFU.  The issue I'm struggling with right now is that the FIFO has up to 64 elements, but it'll add on a CRC16 if there's space.09:20
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