Saturday, 2019-03-23

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futarisIRCcloudBit banging would work, but would be slow. But I guess it would fine for the small SPI flash.00:02
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ewenWhile playing with SB_RGBA_DRV in the Fomu blink example ( I'd expected to be able to influence the mapping of RGB channels to LED colours with .RGB0/.RGB1/.RGB2 parameters to SB_RGBA_DRV.03:05
tpbTitle: fomu-tests/blink at master · im-tomu/fomu-tests · GitHub (at
xobsewen: there might be a nextpnr issue. or maybe they're hardcoded? I noticed something similar.03:06
ewenBut experimentally it seems like while .RGB0/.RGB1/.RGB2 do need to be specified for instantiation to happen, it doesn't seem to matter which order I list led_r/led_b/led_g03:06
ewenxobs: Yeah, that's where I got to: wondering if there was a nextpnr bitstream generation issue going on.03:06
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ewenxobs: I was also trying to figure out the actual *on PCB* mapping of RGB0 / RGB1 / RGB2 to the LED pins (since IIRC you said some were accidentally swapped from schematic).03:07
ewenxobs: Make I create an issue on nextpnr GitHub to see if anyone else has seen this SB_RGBA_DRV behaviour.  Do you want me to tag you too?03:09
xobsewen: yes, please.03:12
xobsOn the PCB, I'd imagine green and blue are swapped.03:12
ewenxobs: According to schematic 39 = Red, 40 = Blue, 41 = Green.  In practice RGB0 = Blue, RGB1 = Red, RGB2 = Green (apparently hard coded).03:15
ewenSo maybe Red / Blue got swapped, and RGB0/1/2 are being hard mapped?03:15
ewenI'll create an issue now (can't seen anything relevant open).03:15
ewenFTR, this seems to be nexpnr commit originally adding SB_RGBA_DRV support:
tpbTitle: iCE40: Bug fixes and general improvement of global network support by smunaut · Pull Request #131 · YosysHQ/nextpnr · GitHub (at
ewen(But I don't understand enough of the nextpnr internals to know if it's trying to map RGB0/1/2 or not.)03:16
ewenFor those playing along at home, this is
tpbTitle: ICE40UP5K-SG48I: SB_RGBA_DRV: LED pin mapping appears hard coded · Issue #254 · YosysHQ/nextpnr · GitHub (at
ewenFWIW, I did wonder if I could test against aranchne-pnr, but as best I can tell it never had ICE40UP5K support added, just the earlier ICE40s.04:17
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ewenxobs: It turns out that arachne-pnr *does* support ICE40UP5K-SG48:
tpbTitle: Project IceStorm (at
ewenAnd after a *bunch* of fiddling I've managed to both build arachne-pnr on the Raspberry Pi image *and* figure out a yosys / arachne-pnr commandline that will run.05:06
ewenarachne-pnr fails to route the design with: fatal error: bad constraint on `led_b': pin 40 does not correspond to RGB driver output `RGB2'05:07
ewenxobs: ... and it works as expected if I swap the RGBn/led_A to be in the order of the output pins.  More detail at
tpbTitle: ICE40UP5K-SG48I: SB_RGBA_DRV: LED pin mapping appears hard coded · Issue #254 · YosysHQ/nextpnr · GitHub (at
ewenxobs: It also looks like the Red and Blue LED connections got swapped in PCB layout, and that we should swap their values in the .pcf files and code accordingly.  Which I think will make everything consistently blue/red/green 39/40/41 RGB0/RGB1/RGB2.05:28
xobsewen: I suppose I could update the schematics. Since it's purely a notational issue.05:33
ewenxobs: It's probably a good idea to update the schematics to match the PCB layout *anyone* to avoid confusion.05:37
ewenBut in addition to the notational issue, there's the consistency with the colour of the visible light... :-)05:38
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tntewen: The RGB0/1/2 connections in HDL are purely cosmetic. They are hardwired in the the silicon to matching pads and can't be changed.06:10
ewentnt: Thanks, it's very useful to have confimation that's the way its implemented.06:11
ewen(Having parameters which "don't do anything" is puzzling, especially in nextpnr which doesn't warn about it.)06:11
tntit's for compatibility with lattice docs, we need to accept those connections, but the doc from lattic is quite clear that they are hw connections and map to the RGB0/1/2 pins of the fpga.06:13
ewentnt: Compatibility with existing code makes sense.  I suspect the arachne-pnr solution of erroring (or at least warning) if you try to connect them to something else is probably the best that can be done to avoid confusion given the Lattice docs / Lattice silicon combination.06:14
tntSure, feel free to submit a pull request to do that06:15
ewenI've added to the ticket with cut'n'paste of your answers so it's in one place.06:19
tpbTitle: ICE40UP5K-SG48I: SB_RGBA_DRV: LED pin mapping appears hard coded · Issue #254 · YosysHQ/nextpnr · GitHub (at
ewenToday is the first I've looked *inside* nextpnr code, so it'd take me a non-trivial amount of time to even figure out where to change it to add an appropriate warning... :-)06:19
xobsI guess the alternative is to lie and swap the connections in the pnr tool, but then you wouldn't have compatibility.06:23
ewenxobs: I guess you could swap around *both* the RGBnPWM *and* RGBn mappigs together, and it'd be internally consistent in the design.  But, as you say not compatible with other code that assumes the fixed mapping.  Bug-for-bug compatibility is hard...06:26
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tntI don't get why this is such an issue ... I mean the input to the SB_RGBA_DRV are from the fabric, just swap that as you need.06:31
ewentnt: It was only an issue for me because I was confused why there were parameters that nextpnr seemed to accept but they (a) did nothing when I swapped them, and (b) I didn't see any errors/warnings.06:34
ewenSo violation of "principle of least surprise" mostly :-)06:34
ewenAs you say, for a real design it's trivial to arrange to swap things over earlier.06:34
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