Friday, 2019-03-22

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mithroxobs: Damn about the boards02:59
mithroxobs: Do have ideas around the NVCM02:59
mithroxobs: How is the conference in Europe going / gone?02:59
xobsmithro: my idea for NVCM was to see what the "Secure load" tickbox did in Icecube.  I have no idea where to go from there.03:43
xobsReally sucks about the boards, though.03:43
xobsFSiC in Europe was good! Met lots of interesting people, and got a mini-lesson in SpinalHDL.03:44
xobsmithro: the only blocking issue I have right now for Foboot is a SPI block, which shouldn't be too difficult to make, especially if I adapt the one from litex.03:46
xobsI'm thinking I'll have a single register that sets CS manually, then a configuration register, an 8-bit "last value" register, and an 8-bit "write data" register that sends data out and updates the "last value" register.03:47
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MadHackerxobs: Needs some way to indicate busy status.08:44
MadHackerIt takes a while to shift out 8 bits if you need to run it slowish at all.08:44
MadHackerSo no writes to write data until it's done; alternatively, FIFO or blocking writes?08:44
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ppisatifomu question: i read it has 128KB of ram, is that bram or external sram? and how much of that is left when the risc-v core is synthesized?09:37
xobsppisati: It has 128 kB of single-ported SRAM, separate from BRAM.  100% (or 0%) is left after the RISC-V core is synthesized.09:38
xobsI.e. it's not used for buffers or the register file, which goes in a separate 16 kB BRAM block.09:39
ppisatixobs: awesome, thanks10:02
tntxobs: I'm working on adding support for the hard spi IP to nextpnr, that might be useful :p10:12
xobstnt: super useful!  I forgot that existed.10:13
xobsLooks like it's only 1-bit, which might be an argument for coming up with a Verilog SPI block, though.10:16
tntYeah, it's not QSPI or anything. If you want a more advanced one, there is the one in the picorv32 repo.10:17
tpbTitle: picorv32/spimemio.v at master · cliffordwolf/picorv32 · GitHub (at
xobsSuper fancy.10:19
xobsI've got the SPI module from _florent_ wired up to a Verilog test bench, and I'm trying to understand how it works.  I think this'll get me the basics.10:19
xobsOnce I have that, the fomu-flash code should be super simple to port over.10:20
xobsOh, wait, spiflash is the file I should be looking at, not spimemio. Even better.10:21
xobsThanks, tnt!10:21
tntspiflash is a verilog model of a spi flash chip for simulation.10:23
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xobsI think I see how it works.10:40
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mithroxobs: Why not start with bit banging?18:34
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