Tuesday, 2019-03-12

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futarisIRCcloudInteresting to read up on UF2. Never used it before. DFU will be the easiest to implement, I think.  Will JTAG over USB fit in the fomu?00:15
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mithroxobs: Just wanted to make sure that you understood that the issue with rx is not got anything to do with the 48MHz and 12MHz alignment - but has to do with the 12MHz locally verse 12MHz at the sender03:50
mithroxobs: Was tnt's fix enough to get you unstuck?03:53
xobsmithro: yes, I'm unstuck now.  Hooray!03:55
xobstnt: there isn't a "final" board, but the DVT board (which is what I posted pictures of yesterday) is up at https://github.com/im-tomu/fomu-hardware/tree/dvt03:57
tpbTitle: GitHub - im-tomu/fomu-hardware at dvt (at github.com)03:57
xobsUnfortunately I'm traveling now, so I won't be able to /test/ the DVT board until next week.03:59
mithroxobs: I'm surprised that tnt's option meet timing...04:05
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xobsmithro: Info: Max frequency for clock 'clk48_1': 54.64 MHz (PASS at 48.00 MHz)04:10
xobsSo not a ton of headroom, but it passes, and works.04:10
mithroxobs: Working better than not04:11
xobsfutarisIRCcloud: Is there an actual JTAG-over-USB spec?  My plan is to implement Ehterbone-over-USB, which will naturally give us Vexriscv debugging.04:11
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xobsOf course, that means I'll need to fit debugging in there as well, which might not meet timing anymore.  I'll look at using one of the smaller Vex cores at that point, though.04:14
futarisIRCcloudxobs: I don't know of an actual JTAG-over-USB spec.04:23
mithroxobs: I'd ask whitequark04:47
futarisIRCcloudxobs: glasgow probably has a standard way of doing things...05:28
xobsfutarisIRCcloud: doesn't Glasgow have a serial chip on it?05:29
futarisIRCcloudxobs: FX2 fifo.05:31
xobsThen you could use the litex Wishbone to uart bridge to get debugging. But you're right, I wonder what other options they have.05:33
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tntxobs: I was looking at the DVT schematic. But given the clock pin you use, you can't use the PLL feature of outputting both the input clock and the generated clock. That only works if the clock comes from the IO site colocated with the PLL.07:21
xobstnt: hmm... which pin would that be?07:24
xobsWild guess: B3 (IOt_46b_G0)07:25
tntyup07:25
xobsThat's a hard pin to hit.07:25
tntBut well, if you can live with slight offset you can leave it as is. You get the 12M on a global buffer, then the PLL takes the input from that (through a tiny bit of fabric routing) and generates the 48M and you can still use both clocks just fine.07:27
tntIt works right now ... so ...07:28
xobsYeah, and 1.6ns isn't too bad.  It Works.07:28
xobsIt remains to be seen how reliable it is, though.07:28
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mithroThe 48MHz <-> 12MHz relationship shouldn't matter?16:53
xobsIt shouldn't, so I'm going to try removing the pll.16:55
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tntYou might need to check how you're crossing the TX side from 12 to 48. Ideally make sure you sample it the 48 MHz closest to the 12 MHz falling edge.17:00
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xobsWell that's not a thing I was expecting to see.  I'm trying some of the more modern, abbreviated Vexriscv cores.21:10
xobsWith no mul/div, I've got it down to 70%: "Info:            ICESTORM_LC:  3720/ 5280    70%"21:11
xobsBut now the critical path is super long.  "Info: Max frequency for clock   'clk12': 13.88 MHz (PASS at 12.00 MHz)"21:11
tntWell it still passes21:17
tntI'd be curious to have a hierarchical usage report.21:18
xobsThe critical path looks like it's a 32-bit shifter, maybe?21:18
tntI would hope that the small vexrisc would use an iterative shifter and not a full-barel one.21:19
xobsIt does use an iterative shifter.21:20
mithroxobs: With the USB?21:25
xobsmithro: With the USB.21:25
mithroxobs: That is the level I was expecting to see us at with USB+VexRISCV21:26
mithro~3500 LC was my guesstimate...21:26
xobsThe multiplier and divider are pretty large.  And the DebugPlugin doesn't currently work the reduced pipeline count.21:26
mithroYeah, definitely want to disable multiple and divide if not using DSP blocks21:27
xobsI don't actually see any option to use the DSP blocks for multiplication.  I see it mentioned in the readme, but I don't see them actually used anywhere.21:28
mithroI think it might not have been merged back from https://github.com/SpinalHDL/VexRiscvSoftcoreContest2018 ?21:29
tpbTitle: GitHub - SpinalHDL/VexRiscvSoftcoreContest2018 (at github.com)21:29
xobsThat's the repo I'm looking at now, and I don't actually see anything in there relating to DSP blocks.21:29
xobsIt looks like it's using the normal MulPlugin for the Up5kPerf and Up5kArea cores.21:31
mithroIt does say "1 cycles multiplication using FPGA DSP blocks (result in the writeback stage)" -- but maybe that is only on the Igloo2 part?21:31
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xobsNo, Igloo is also using the normal MulPlugin21:32
mithrohttps://github.com/SpinalHDL/VexRiscvSoftcoreContest2018/search?q=dsp&unscoped_q=dsp21:33
tpbTitle: Search · dsp · GitHub (at github.com)21:33
xobsIt's getting inferred, maybe?21:34
mithroxobs: Oh, it might only work with the proprietary tools...21:36
mithrohttps://github.com/YosysHQ/yosys/commit/03aa3541aeff0ff372672f553c114fb4146c785821:36
tpbTitle: Merge pull request #786 from YosysHQ/pmgen · YosysHQ/[email protected] · GitHub (at github.com)21:36
xobsOn ICE40, I think the block is called SB_MAC16, which is only mentioned in the simulation library.21:36
xobsOhh, DSP != MAC16...21:37
mithroxobs: MAC16 would be the DSP block in the ice40?21:39
xobsI mean, I did find this: https://github.com/TheRoboticsClub/2018-colab-DavidLobato/blob/be32a0b72e5d21005168e4d67b365a09b98bb17d/SpinalHDLExamples/src/main/scala/examples/multiply8x8/Multiply8x8.scala21:40
tpbTitle: 2018-colab-DavidLobato/Multiply8x8.scala at be32a0b72e5d21005168e4d67b365a09b98bb17d · TheRoboticsClub/2018-colab-DavidLobato · GitHub (at github.com)21:40
mithroxobs: Why don't you log an issue on the repo and see what they say?21:44
xobsThat's a good idea.21:45
xobsI need to figure out how to hook up USB to Wishbone, but a two-stage Vexriscv without a mul/div, but WITH debug, comes out to: "Info:            ICESTORM_LC:  3944/ 5280    74%"22:12
xobsAnd, most concerningly: "Info: Max frequency for clock   'clk12': 12.58 MHz (PASS at 12.00 MHz)"22:13
xobsWell, I think that's a problem for another day.  I'm pleased with how this is going.22:14
tntxobs: What's the usage of Vex by itself ? (without usb)22:15
xobsOoh, good question.  Especially since the USB core hasn't been really optimized yet.22:16
xobsInfo:            ICESTORM_LC:  2835/ 5280    53%22:16
xobsThat's with the debug bus enabled.  That seems high, but it includes the CPU, wishbone, the UART, timer, CSR block, and whatever the "ctrl" block is.22:18
tntOnly ~ 1100 LCs for the usb core. Not bad.22:19
xobsOh, and the interrupt controller.22:21
xobsDebug is, apparently, only 35 LCs.22:21
mithroxobs: I would expect the final USB core to be around ~1000 LCs22:22
tntDoes its size depends on the # of EPs ?22:24
mithrotnt: I would expect so22:24
xobsThis is with just EP022:26
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xobsApparently the MulPlugin is supposed to be inferred, but it's not working yet with yosys.22:32
tntthere is an option to synth40 to allow DSP inferrence.22:32
tnt-dsp22:33
xobsMust be new.  Was it added by that patch mithro mentioned?22:34
tntIt was added a couple weeks ago I think.22:34
xobsOkay, I'll have to see what it takes to recompile Yosys then.  I think I need an msys2 install.  Or maybe I can do it on my server.  Or under WSL.22:36
xobsI also need to file a bug about allowing MulPlugin and DivPlugin on designs without a Writeback or Memory stage.22:36
xobsI also probably should sleep.  I've been travelling today.22:37
tntYeah, isn't it very late in Singapore ? That's wwhere you are right ?22:37
xobsNormally, yeah.  Good memory.22:38
xobsBut I'm in Prague for tonight, and tomorrow I go to Paris for https://wiki.f-si.org/index.php/FSiC201922:39
tpbTitle: FSiC2019 - F-Si wiki (at wiki.f-si.org)22:39
tntOh, that looks interesting.22:40
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