Tuesday, 2019-03-05

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mithrotnt: If you want to include the program in the bitstream, you only have a small amount of space...00:00
tntmithro: ah yeah. I solved that by having a tiny spi reader that populates the spram then releases the picrorv32 resets.00:01
mithrotnt: We were looking at if there is an option to store in the nvcm as a failsafe bootloader00:02
tntAh yeah, right, I remember that.00:03
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xobsmithro: lots of little things.  The output pipeline has a three-cycle delay (state transition to SENDING, filling the shift register, and filling the bit stuffer).  I hoisted the "start sending" to an earlier state and created a sync pulse generator that eliminated those delays.00:42
xobsThere were also a ton of CDC shift registers, which shouldn't be required if usb_12 and usb_48 are derived from the same clock source and are synchronous.00:42
tntxobs: I'm kind of curious is you manage to repond within the 6.5 bit time spec of if you're a bit longer ?00:43
xobsI'm going to re-install the unififo today and see if I can't figure it out that way.  Use that to tune it so that I get clean signals from the host, then remove the host and send transmissions to an oscilloscope to make sure that it's coming out the way we expect.00:44
xobstnt: hmm? Can you rephrase the question please?00:44
tntxobs: so when the host sent you a packet and you must repond, (bus turn around), you have 6.5 bit to go from the SE0->J transition that the host made to you making a J->K transition.00:46
xobsAs I understand it, you get one more than that, because you get one bit cycle after the SE0->J because it's actually driving "J".00:47
futarisIRCcloudxobs: Is https://github.com/xobs/valentyusb/commits/xobs-usb12 the latest?00:55
tpbTitle: Commits · xobs/valentyusb · GitHub (at github.com)00:55
xobsfutarisIRCcloud: that's the latest version of the hardware, yes.00:56
xobsI should move my git repositories to github...00:57
tntis the sw stack somewhere ?00:57
xobstnt: I'm just putting that together. It's a few disparate repos right now.00:58
tntOk great. Curious to see if I can easily adapt it to my needs :)01:03
xobstnt: you can give https://github.com/xobs/foboot a try. Very untested.  I just merged two repos together.01:26
tpbTitle: GitHub - xobs/foboot: FPGA-half (at github.com)01:26
xobsAlso, I need to rush off now.  Back in about two hours.01:26
xobsIt's still very much in the "me doing experiments" stage.01:28
xobsThe hw dir generates Bitstreams without a valid rom, but you can use the "-l" to switch on fomu-flash to load a replacement rom.01:30
xobs(I really should write this all up, maybe once it's working.)01:40
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xobsOkay, time to get back into it.04:04
xobsSo strange.  `usb_obuf_empty_read()` is 1 (indicating there isn't any more data to read), and `usb_ev_pending_read()` is also 1 (indicating there is more data to read)?05:43
xobsI'm going to make another register and read the number of USB packets that have been received.  That way I know who is lying.05:45
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xobsGuess there's an issue where the "pending" value defaults to 1, and doesn't go to 0 until you actually receive a USB packet.06:58
xobsThe good news is that those lovely SOF packets are fantastic for testing link integrity, and the CRC5 is passing on every packet I receive.  Which means the bit unstuffing is working as it should.06:59
xobsAh. It would help if I only accepted data when the USB block is enabled.  Turns out "SE0" happens an awful lot when the pullup is not enabled, and things aren't getting driven...07:15
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xobsAnd after looking at the output with an oscilloscope, I can determine that the output is completely wrong.  Gues I didn't understand how Migen state machines work.08:46
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MadHackerxobs: "Completely wrong" is at least a reproducible bug with known effects and no intermittent behaviours. :)09:20
xobsMadHacker: That's true!  And I can now whittle away at it.  Hooray.09:21
xobsI think maybe part of the problem is that clk12, which is derived from clk48, is offset by 1/4 of a cycle.10:04
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xobsThat's not it.10:53
xobsThis seems like a metastability problem, which shouldn't happen since these signals come from the same clock.10:54
xobsPlus, something is inserting a transition where there isn't one.  I'm sending all zeroes, but somehow it's adding a 1.10:55
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xobsI think what's going on is that the data that the shifter sees may change on the last bit (or the second-to-last bit) because we're not keeping a copy anymore.11:41
xobsAh, or it could be due to the fact that the NRZI "bit-done" signal is coming from a different clock domain that's slightly offset.11:42
xobsIt's a shame I need to stop debugging this for the night.  I feel that I have many good threads to pull on.  And this is very obviously the reason that the USB stack isn't working like it should.  I think that once I solve this problem, the USB bootloader should come together very quickly.11:43
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tntThe sw/ dir seems to be a mix of a _lot_ of projects :)18:50
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tntDamn, the host are pretty agressive retying SETUP ... like if I didn't have space for it now, I might not have space for it 10us later FFS, just retry on the next frame or so.23:01
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