Tuesday, 2019-02-12

*** tpb has joined #tomu00:00
*** awe00 has quit IRC00:28
xobsAmosSam_: have you used https://www.silabs.com/documents/public/reference-manuals/EFM32HG-RM.pdf00:58
*** imdeni has joined #tomu01:06
*** johnhmay has joined #tomu01:06
futarisIRCcloudxobs: I've used STM32L1 series. Similar market to that EFM32HG, but have a Cortex-M3 instead...01:17
*** andi- has joined #tomu01:30
*** olasd has joined #tomu01:34
*** xkapastel has quit IRC01:42
mithroMadHacker: The edge-tpu is in the 100mW -> 4W space, the iCE40 should be in the <20mW space02:04
mithroMadHacker: https://github.com/SymbioticEDA/MARLANN02:04
tpbTitle: GitHub - SymbioticEDA/MARLANN: Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks (at github.com)02:04
mithroxobs: Sounds like you have a testcase which causes the duplicate byte issue?02:05
xobsmithro: I do, so now I'm working on getting the bitstuffer working.02:05
mithroxobs: What do you mean by "getting the bitstuff working" - you mean make the tests pass?02:06
xobsYeah, trying to make the tests pass and fix the testcase I found.02:07
xobsmithro: I'm starting to understand what you mean by "the tests are broken".  The testcases I found don't work in the testbench, but they don't work in different ways.  I.e. the testcase is "[0xa5, 0xe1, 0x7e]", but the testbench sees "[0xa5, 0x87, 0x7e]" and real hardware sees "[0xa5 0xc1 0xfd 0xfd]".05:09
mithroxobs: what is the "correct" answer05:12
xobs[0xa5, 0xe1, 0x7e]05:12
mithroBtw all the high level tests were working05:13
mithroIs this with your valid change?05:13
xobsNo, I backed that change out.05:14
mithroI'll be back at a computer in like 20mins05:14
mithroHow's the software side going?05:15
xobsI haven't worked on the software side, since I want to get the hardware working first.05:16
xobsAlso, "unifio_test.py" fails all 20 tests on your usb12 branch.  Is that one of the ones that's supposed to pass?05:17
mithroCan't remember, but I think it use to05:18
mithroBack at a computer now05:25
xobsWelcome back05:25
mithroWhat is the status of "python -m valentyusb.usbcore.cpu.epfifo_test -v"05:33
xobsRunning it now...05:34
mithroSo far it mostly seems to be passing for me...05:37
mithroIt is *rather* slow however...05:37
xobsStill running for me, too.  But I think it's passing.05:43
mithroxobs: python -m valentyusb.usbcore.rx.pipeline_test -v05:56
xobsmithro: still running the first set of tests05:56
mithroxobs: Open a new terminal and run another one :-P05:56
xobsRan 1 test in 34.613s05:58
xobsOnce this test is finished, I'm going to see if I can spot these defective SOF frames in the vcd files.06:02
xobsOkay, good.  That finished (3022s) without errors.  Now I'm going to do that SOF test.06:29
xobsmithro: The test I added at https://github.com/xobs/valentyusb/commit/8347ac8d25118a560ab1e4714df39f583d66f8a8 has some strange values in the vcd files.  For example, I do self.send_sof_packet(150) which should send [0xa5, 0x12, 0xc5], but the vcd files shows usb_core_rx_o_data_payload[] as being [0xa5, 0x12, 0xd8]06:40
tpbTitle: usbcore: test: add sof packet test · xobs/[email protected] · GitHub (at github.com)06:40
xobsThat's funny.  If I make the last byte of an SOF "0x55", then it works.06:52
mithroxobs: I'm afraid I've run out of steam today07:33
mithroWoke up way to early this morning and also got new glasses which are taking a while to get use too....07:33
xobsmithro: No worries.  I've gotten distracted looking at the CRC5 stuff, which I think is the source of the problems in the VCD files.07:34
mithroxobs: Oh?07:34
xobsYeah, if I import crc5_sof and use it directly, I get values that differ from what I'm seeing in the LA.07:35
xobsFor example, hex(crc5_sof(213)) yields 0x1b, but in the Beagle LA it shows the CRC should be 0x16.07:35
mithroxobs: BTW This commit looks very suspect -> https://github.com/mithro/valentyusb/commit/28311625e914b87921ea3e06a27cb36835b31aae07:35
tpbTitle: What is this for? · mithro/[email protected] · GitHub (at github.com)07:35
mithroxobs: Unrelated to your crc5 issue...07:36
tpbTitle: valentyusb/packet.py at usb12 · mithro/valentyusb · GitHub (at github.com)07:36
mithroxobs: I'd play with some doctests there07:37
xobsI'm not sure what a doctest is, but I'm trying to come up with a known-good crc5 implementation that I can use to compare those comments with what they should be.07:38
mithroxobs: python -m valentyusb.usbcore.utils.packet -v07:38
mithroxobs: See those comments at the top of each function are actual tests you can run -> https://github.com/mithro/valentyusb/blob/usb12/valentyusb/usbcore/utils/packet.py#L72-L7507:38
tpbTitle: valentyusb/packet.py at usb12 · mithro/valentyusb · GitHub (at github.com)07:38
tpbTitle: Python Tutorial: Tests, DocTests, UnitTests (at www.python-course.eu)07:39
tpbTitle: doctest — Testing Through Documentation PyMOTW 3 (at pymotw.com)07:39
tpbTitle: doctest introduction - Python Testing (at pythontesting.net)07:40
mithrohttps://en.wikipedia.org/wiki/Doctest :-P07:40
tpbTitle: doctest - Wikipedia (at en.wikipedia.org)07:40
mithroxobs: IE I'm too lazy to write both documentation and tests for functions like that at the same time :-P07:40
xobsI see.07:40
xobs8 failures.07:40
xobsWait, 5 of those were me breaking things.  3 failures.07:41
mithroxobs: be careful of endian issues08:51
mithroxobs: MSB verse LSB has bitten me multiple times here08:51
xobsmithro: I'm running into that a lot. So difficult.08:52
mithroIt's why I spent ages working on the pprint module08:52
mithroReally should have spent the effort on doing a bits type08:54
mithroI think there are like ~3 half arsed efforts in ValentyUSB :-P08:55
mithroWell, I'm probably going to call it an early night08:57
xobsI'm just trying all possibilities.08:59
*** AmosSam has left #tomu09:48
*** AmosSam has joined #tomu09:54
*** awe00 has joined #tomu10:48
xobsSuch a fuzzy yak.11:13
xobsUSB is reverse-endian, which I guess kinda makes sense for a wire protocol.  So it writes binary 1 as "0b10000"11:14
*** futarisIRCcloud has quit IRC11:20
*** futarisIRCcloud has joined #tomu11:24
futarisIRCcloudEndianness usually refers to the byte order. Least significant bit first. Ethernet and RS-232 are the same order.11:29
MadHackerActually, USB's the odd one out here then. That's little-endian.12:09
xobsAs usual, though, 4 hours of work that boils down to a two-line patch.12:12
MadHackerYup. :/12:14
MadHackerAh well. Could be worse. VAX bi-endian is no longer a thing.12:14
MadHackerOr, well, middle-endian really.12:14
xobsNeither is Cray, which I seem to recall was also mixed.12:15
MadHackerNo more NUXI problem.12:15
*** futarisIRCcloud has quit IRC13:40
*** AmosSam has left #tomu15:34
*** AmosSam has joined #tomu15:36
*** awe00 has quit IRC15:56
*** awe00 has joined #tomu16:09
*** xkapastel has joined #tomu16:28
*** awe00 has quit IRC17:01
*** awe00 has joined #tomu17:08
*** awe00 has quit IRC17:17
*** alexhw has quit IRC17:24
*** awe00 has joined #tomu17:25
*** alexhw has joined #tomu17:26
*** alexhw has quit IRC17:30
*** alexhw has joined #tomu17:31
*** TheJJ has quit IRC17:41
*** mifune has quit IRC17:41
*** TheJJ has joined #tomu17:42
*** AmosSam has left #tomu18:06
*** AmosSam has joined #tomu18:08
*** AmosSam_ has joined #tomu18:27
*** AmosSam_ has quit IRC18:56
*** awe00 has quit IRC18:58
*** kuldeep_ has joined #tomu19:10
*** andi- has quit IRC19:11
*** jayvee has quit IRC19:11
*** kuldeep has quit IRC19:11
*** kuldeep_ has quit IRC19:12
*** kuldeep has joined #tomu19:12
*** jayvee has joined #tomu19:13
*** andi- has joined #tomu19:16
*** mifune has joined #tomu19:22
*** AmosSam_ has joined #tomu19:36
*** AmosSam_ has quit IRC19:49
*** awe00 has joined #tomu20:22
*** AmosSam_ has joined #tomu20:54
*** AmosSam_ has quit IRC21:13
*** jayvee has quit IRC21:13
*** AmosSam_ has joined #tomu21:13
*** jayvee has joined #tomu21:14
*** lathiat has quit IRC22:41
*** futarisIRCcloud has joined #tomu23:13
*** AmosSam_ has quit IRC23:32
*** awe00 has quit IRC23:51

Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!