Monday, 2019-01-21

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nats`mithro, could you point me what I have to do to port timvideos to genesys2 in that case ?09:14
nats`because i'm not sure what's missing09:14
mithronats`: create platform/ then create targets/genesys2/....09:16
nats`but why we don't take the one from litex ?09:16
nats`there is something I don't get09:16
mithronats`: Probably start with, then, etc09:16
tpbTitle: litex-buildenv/ at master · timvideos/litex-buildenv · GitHub (at
nats`I took a look at that I used that to start the porting but you pointed that it already exists in an other repo09:18
nats`my point is why we don't get it from that repo ?09:18
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at
nats`I have almost the same and I need to finish the HPC09:36
nats`so exactly the same status09:36
nats`maybe i should finish what's already started more than reworking everything09:37
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mithronats`: Sorry got distracted10:28
mithronats`: The reason we don't reuse the one from litex is a bit historical10:28
mithronats`: Maybe we need revisit how to do that10:29
mithronats`: I know that cr1901_modern has opinions on that :-P10:29
nats`uhhmm ok I'll wait for result of that thinking :D10:50
nats`I don't want to be in the middle of a 'political' war :D10:51
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mithronats`: It's more of nobody has had the time to clean it up, get our changes upstream and check that it doesn't break things10:56
mithroI think the biggest blocker is cleaning up the spi module stuff10:58
mithro    # Micron N25Q128 (ID 0x0018ba20)10:59
mithro    # FIXME: Create a "spi flash module" object in the same way we have SDRAM10:59
mithro    # module objects.10:59
_florent_mithro, nats: i need to keep some platforms in litex for regression testing and the projects i'm working on, but you are free to copy platforms and or targets from litex to litex-buildenv11:05
mithronats`: So, no big deal to copy11:06
nats`cool ok11:12
cr1901_modernmithro, nats: Relevant issue is here: Fixing this issue has taken a backseat for me for various reasons.11:13
tpbTitle: Reunite `litex-buildenv` with LiteX platforms · Issue #28 · timvideos/litex-buildenv · GitHub (at
mithro woot!11:17
nats`I should do that with my HDMI2 core I guess11:19
nats`but it uses GTP from artix...11:19
felix_why verilog and not (n)migen? /o\11:21
cr1901_modernLearning a language == time commitment, he may want to limit the uncertainty of things going wrong on this project by using what he's used to11:24
daveshahVHDL -> Verilog is easier than VHDL -> Migen I suspect11:25
daveshahCertainly when doing my CSI-2 receiver it was quite mechanical to take it to Verilog11:25
nats`and at least verilog is really used everywhere and pretty generic11:26
felix_yeah, migen is quite different to vhdl/verilog and it took me quite a while to get used to it. verilog is a horrible language though...11:26
nats`uhhmm I still can't opensource my HDMI2 core.... the documentation is still not public :|11:27
nats`there are shitty part in HDMI2 making things complicated to opensource without taking some risk11:27
daveshahIt is leaked at least now11:29
nats`sure but I'm not sure it's a good idea11:30
nats`the hdmi forum can be really agressiv11:30
nats`I worked in a related field for few years and they are not the kind of "nice guy"11:30
nats`anyway the only big difference is in fact the scrambling system to activate once you go higher than 300MHz clock11:31
daveshahThere's a reason the ULX3S FPGA boards are being sold with "GPDI" connectors11:31
nats`and the fact that you need to divide clock at those rate too11:31
nats`hehe nice rename :)11:31
cr1901_modernGeneral Purpose Differential Interface?11:32
daveshah> GPDI is General Purpose Differential Interface, Electrically LVDS, mostly TMDS tolerant female receptacle more-or-less compatible with digital monitors/TVs11:32
nats`I'm wondering how this pdf was cleaning11:33
nats`the one I have is watermarked with the name of my former boss company11:33
nats`was cleaned11:33
daveshahDewatermarking is quite common in this world...11:34
cr1901_modernWell for those who pirate photoshop anyway11:34
nats`oky I'm not aware of all those tricks :)11:35
tpbTitle: Display Industry Standards and Specifications (at
daveshahGrab em before they go11:36
cr1901_modernI suggest wget's --mirror option :)11:36
cr1901_modern(No don't, that's actually rather inconsiderate)11:36
nats`those were my test :)11:37
nats`and I managed to do that on artix 7 with timing in the tens of picosecond range11:37
daveshahI did 4k30 DVI once from an old Xilinx devboard, with a 4k TV via HDMI adapter (effectively 1.4)11:37
daveshahThis was using the parallel to DVI chip onboard11:37
daveshahRunning said chip at about twice its rated maximum pixel clock11:38
daveshahSurprisingly, that ran rock solid but got a bit warm11:38
nats`not that surprising in fac t:)11:38
nats`DVI/HDMI are really tolerant11:38
nats`I managed to get a working signal with something like 5x less amplitude11:38
daveshahYeah, I was most surprised that the PLL in that chip was able to lock at 2x its expected upper frequency11:39
nats`uhhmmm did you actually test that assumption :D11:40
nats`I ask because in fact on a lot of screen I managed to get a picture with clock at a lower rate :)11:41
nats`(still integer multiple)11:41
daveshahYes it was definitely running at the proper rate11:41
nats`so 297MHz or something like that vs 148.5 ?11:42
nats`that's pretty impressive indeed :)11:42
daveshahConnected to a camera running at 4k30 too11:43
nats`in fpga the main problem is their weird running sum11:43
nats`it makes that point hard to pipeline because you have dependencies between pixel11:43
nats`and when you work with GTP you have to pack the pixel 4by 4 on each lane11:44
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