Friday, 2019-01-18

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xobsmithro: I get there on Sunday.00:08
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xobsI should arrive at around noon. Though I'm still unsure of how I'm getting from the airport...00:09
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micolous[m]@xo There's transit instructions on the wiki and a list of peoples' flights that are arriving around the same time00:42
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xobsmicolous: true! but there aren't many international flights around my time, taxis are expensive, and buses are expensive and infrquent. I need to pick which one is best.01:01
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mithroxobs: Go jump on a flight now and we will pick you up from the airport tomorrow :-P01:49
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ewenmithro: would vcd file names called something like work for you?02:04
ewen(Currently I'm thinking our base test class ends up with a make_vcd_name() that builds the full filename, rather than repeating that everywhere.)02:05
mithroewen: SGTM02:05
mithroewen: I think the multi-clock domain base we need is02:06
tpbTitle: Snippet | IRCCloud (at
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xobsmithro: still have to pack, and I'm fighting with Debian packaging at the moment :)02:17
cr1901_modernIs there a party or something?02:17
xobsSpeaking of which, nextpnr is huge! The binary is 179 MB stripped.02:18
cr1901_modernIs this w/ the GUI?02:18
xobscr1901_modern: no gui, on arm, just python02:19
mithroxobs: Hrm...02:19
xobsAh, the chipdb files are linked in, and each one is huge.02:20
cr1901_modernoh right that sounds about right02:20
xobsnextpnr_ice40::chipdb_blob_8k is 89 MB, for example.02:20
xobsAt least they compress nicely.02:20
cr1901_modernit's a tradeoff of having a flat db vs a db for each chip. Or something02:20
mithroxobs: 52.8 MB02:20
mithroI think the chipdb could be as little at ~10-15k02:22
xobsYeah, it's mostly zeroes.02:23
mithroIt should be *super* compressible due to being tilable02:24
mithroewen: That pull request looks pretty good to me03:16
ewenmithro: Cool, I'll carry on and convert tx/ and rx/ then.03:18
ewenmithro: Yes, I started with the idea of putting run_simulation() into one of the base classes.  But pulled it out as I realised we could do make_vcd_name() as a simpler change for this bit.03:20
mithroewen: Yeah, small changes seems good03:20
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CarlFKxobs: mithro: you just get pre-release version of the av-spam - can you look for it and tell me if looks ok?03:43
xobsCarlFK ( looks good. Though, and you might get this question a lot, what if I want a different poster image? My slides are ever so slightly different.03:59
mithroposter image?04:00
xobsmithro: "The video will start with the following image:"04:01
xobsCarlFK ( also, minor nit, but the opening paragraph says "event organizers" but the Commonwealth spelling is "organisers".04:02
mithroewen: tell me when you want me to review it again04:06
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mithroewen: Is the newline in the description argument to setup() causing the markdown render failure something that should be either logged as bug of if "working as intended" and there should add something to the docs...04:25
mithrorohitksingh_work: ping?04:25
rohitksingh_workmithro: pong!04:26
ewenmithro: I have a feeling that I read somewhere that Summary: (ie, description=) was documented to be a *single* line description.04:30
ewenmithro: But the *effect* of it being multi-line is definitely "weird".04:30
ewenmithro: Re vcd filenames, I'm still working on it.  Just converted tx/ over, still need to do rx/.  Will ping you when I'm done updating.04:32
rohitksingh_workmithro: Mimas A7 has FT2232H, so it is possible to stream mpeg frames over it at (but it's bulk endpoint, so no guaranteed bandwidth). Other option is to create a carrier/module for it.04:59
rohitksingh_workbtw Mimas A7 has 6 locations where pmods can be directly connected, but you cannot use all 6 probably at the same time...max 4 can use at the same time05:01
CarlFKxobs: I hear the conf told the presenters they need to use that image/svg as part of your presentation.   which is .. im not sure how to say it nicely ;)05:01
CarlFKand the answer to "I want.." is "tell us what you want, we will let you know who's problem that is."05:02
xobsCarlFK: that's true, and that's what I did, but they assume you're using LibreOffice, which I have lots of problems with.  So I'm using reveal.js, and naturally the title slide is ever-so-slightly different.05:03
CarlFKlooking over all the titles, I see many that have wonky capitalizations05:03
CarlFKI suspect you can ignore that "change your pres..." directive and no one will even notice05:04
ewenmithro: Finally done all the changes I planned for  Feel free to review when you get a chance.05:07
tpbTitle: Sign in to GitHub · GitHub (at
ewenmithro: Of note, I've prescriptively converted all vcd output filenames to be consistently SUBDIR.SUBDIR.MODULE.something, and for most the something is the testclass (except the ones you were generating tests out of a dict, array, etc which had sequence numbers).05:09
rohitksingh_workmithro: Pmod compatible locations
tpbTitle: Dropbox - mimas_a7_pmods.png (at
xobsmithro: debian packages:
tpbTitle: fomu-pi-gen/fomu/04-fomu/files at master · im-tomu/fomu-pi-gen · GitHub (at
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ewenmithro: Re newline in description, I'm struggling to find better documentation than which advises "description is a short, one-sentence summary of the package".  So possibly under-documented that it *needs* to be a single line.  Not just single sentence.05:42
tpbTitle: Packaging Python Projects Python Packaging User Guide (at
CarlFKmithro:  Error-Details: #7: gstjpegdec.c(1194): gst_jpeg_dec_handle_frame (): /GstPipeline:pipeline005:50
mithroCarlFK: need a bit more than that, what does dmesg show? I assume you are trying to stream the pattern? What version / image? Is the encoder enabled?05:51
CarlFKmithro: git describe: v0.0.4-453-gfd68613  built: Dec 29 2018 03:49:0205:52
tumbleweedmithro: also, it's outputting some green garbage on the HDMI output05:56
mithrotumbleweed: Sounds like something is broken05:57
tumbleweedOK, only when it's sent to a TV05:59
CarlFKmithro: green garbage seems to be the TVs problem.06:02
CarlFKmithro: ssh [email protected]06:15
CarlFKmithro: nothing interesting dmesg: [ 4977.516425] uvcvideo: Found UVC 1.00 device - Numato Opsis Board (2a19:5442)06:15
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CarlFKmithro: Decode error #62: Invalid JPEG file structure: SOS before SOF07:11
CarlFKDecode error #8: Bogus Huffman table definition07:12
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CarlFKgst-launch-1.0 v4l2src device=/dev/video0 ! jpegdec ! fakesink07:26
ewenmithro: re VCD and GtkWave, and particularly look interesting.  The latter seems to help create *.gtkw save files for GtkWave that load the VCD file.07:30
tpbTitle: pyvcd · PyPI (at
ewenmithro: Also (from AFAICT) can do basic reading of VCD files (eg, to find the embedded signals).07:41
tpbTitle: Verilog_VCD · PyPI (at
mithroewen: I think whitequark tweeted about some VCD library from SanDisk I think?07:57
mithroewen: Oh that was the first one you linked :-P07:58
ewenmithro: The thing I'm trying to figure out is how to get the signal names from the simulation to give to the vcd.gtkw to write into the file list to load...08:00
ewen(looks like some of them are self.FOO attributes on the dut, and others seem to magically appear elsewhere).08:00
ewenmithro: I'm suspecting the easiest way is going to be to parse the VCD file back off the disk to find out what is inside it, and then write the gtkw file using those.  Because at present the best view of the signals I can see is *inside* the Simulator class.  And since we're using run_simulator() we never see that Simulator class.08:06
ewenHmm, run_simulation() is trivial.  So we could perhaps replace that, and hang onto the Simulation longer.08:09
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mithroewen: The thing with the ClockDomainRenamer and other things mangling the names is causing me the most grief at the moment08:36
ewenmithro: Can you point me at some more context for that ClockDomainRenamer?08:41
ewen(I've read enough of the migen sim code node to have an idea how it works internally.)08:41
mithroewen: Looks like it comes from[email protected]/msg00268.html08:42
tpbTitle: [M-Labs devel] [PATCH] fhdl/decorators: make the transform logic more idiomatic (at
tpbTitle: migen/ at master · m-labs/migen · GitHub (at
mithroewen: look at the pipeline tests I think...08:44
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mithroHi bunnie!08:51
ewenmithro: Thanks.  I'll try to have a look at that tomorrow.  (About to head back to dorms for sleep.)08:51
mithrobunnie: Can you just enter the env and then run pycharm?08:54
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mithrobunnie: Sorry, got distracted and didn't realize you were talking to me10:00
mithrobunnie: Sould prefix lines with my nick if you want me to response10:00
mithrobunnie: Yeah - litex-buildenv has a weird mix of Makefile + Python10:04
mithronats`: I'm more than happy to send you a NeTV2 board if you have time to contribute to that10:10
nats`sure why not we can discuss whta should be done on it before so i can evaluate how well I would be placed to get it and work on it10:11
nats`evaluating time needed basically :)10:11
mithronats`: rohitksingh_wor1 and _florent_ would likely be good people to help you10:11
mithronats`: rohitksingh_wor1 has just been working on getting the Mimas A7 support into LiteX-BuildEnv10:12
nats`oky like i said I can take a first look for genesys 210:12
mithronats`: Yeah, that seems like a great starting point10:12
nats`do you have anything zynq based too like parallela ?10:12
mithronats`: Not yet, LiteX doesn't really have good AXI / hard processor support yet10:13
nats`oky no problem :)10:13
mithroI believe that _florent_ and felix_  might be working on things related to that...10:13
nats`I'll focus on genesys 210:13
mithroHaving a supported & working Kintex 7 platform would be really awesome10:14
mithrobunnie: which part?10:25
mithrobunnie: Which args are you changing where?10:27
mithrobunnie: There is a "make env" and "make info" which will output various info10:28
mithrobunnie: Also "make V=1" will print the full command lines being run IIRC?10:28
mithrobunnie: print mainly? :-P10:28
mithrobunnie: Pretty much everything goes via the file10:29
tpbTitle: litex-buildenv/ at master · timvideos/litex-buildenv · GitHub (at
mithrobunnie: I rarely use a debugger with Python10:29
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randomrandomxobs: What about this?11:03
xobsrandomrandom: hello, that works11:03
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mithroxobs: Needed to do a /mode #timvideos -q $~a11:04
xobsirc modes are mysterious11:04
mithroYes they are...11:05
mithroAnyway bed time for me11:05
bunnieok, i got pycharm to work. the trick was I had to quit and close *all* my other projects before trying to open litex-buildenv for the first time. The moment I closed all the windows, litex-buildenv just popped up. And then of course I had to run a set of scripts to establish the conda environment, paths, and using make V=1 to get the command line specific to my build but now it seems to be working.11:05
mithrobunnie: Oh cool! Probably some shared state or something11:08
mithrobunnie: You'll have to teach be about the debugger sometime :-P11:08
bunnieit's positively luxurious to be able to hit a breakpoint and see the full state of the program.11:17
bunniei learn so much, especially about variables that i didn't even know existed.11:18
xobsI'm still trying to get that in vscode. The ability is there, it's just that migen breaks the language server right now.11:20
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rohitksingh_workI also use pycharm debugger to find out and debug migen bugs :p13:01
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bunniebtw, anybody got an ICE40 reference design using migen that also uses a PLL? nextpnr is ignoring the sys_clk constraint, claiming the net doesn't exist (but I can see it in the verilog), and then nextpnr errors out saying clock constraints are incomplete...17:44
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daveshahbunnie: unfortunately sometimes a different name for the net can be picked18:08
daveshahRun without any clock constraints first and see what it is called in the timing report18:09
daveshahThere is a heuristic to try and pick the highest level name, or the alphabetically first one if multiple exist at the same level18:09
bunniethanks! I'll give that a try.18:19
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bunnieso, i think i removed the constraints by commenting out the constraints, but I still got an error         self.platform.add_period_constraint(self.crg.sys_clk, 1e9/clk_freq)18:33
bunnieoops that's not it18:33
bunnieWarning: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.18:34
bunniethat one18:34
bunniehowever, i can get it to compile with --force as the argument.18:34
bunniewhen i remove the PLL and just use a SB_GB buffer buffering the clock signal to one of the exact same name as it would have without the PLL, things also seem to work (without --force)18:35
bunnieit also looks like it's somehow picking 12MHz as a clock constraint out of thin air when i don't have any apparently defined?18:35
bunniebasically, the error i get starts with a very long list of ports and the top looks like this:18:37
bunnieInfo: Annotating ports with timing budgets for target frequency 12.00 MHz18:37
bunnieInfo:    remaining fanin includes GLOBAL_BUFFER_OUTPUT (net crg_sys_clk)18:37
bunnieInfo:         driver = SB_GB.GLOBAL_BUFFER_OUTPUT18:37
bunnieInfo:         user: $auto$$10434_DFFLC.CLK18:37
bunnieInfo:         user: $auto$$11078_DFFLC.CLK18:37
bunnieand then ends with the note about "Warning: timing analysis failed due to presence of combinatorial loops, incomplete specifications of timing ports, etc."18:37
bunnieAny tips on how I might start to debug a problem like this? or should I just keep on using --force and ignore the error.18:38
daveshahThe 12MHz constraint is a default (some internal algorithms need a frequency to work) for clocks without a constraint, set using the `--freq` command line argument18:49
daveshahThe most useful thing to do is put a netlist somewhere where I can look at it. It seems like this is something broken around the PLL18:50
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bunniesure, here's a copy of my gateware directory:
tpbTitle: Index of /bunnie/gateware (at
daveshahCoincidentally I think I just found the problem19:13
bunnieoh cool19:13
daveshahyou have a global buffer connected to PLLOUTGLOBAL19:13
daveshahthis is not incorrect, but also not a useful pattern (hence hit an edge case in nextpnr)19:14
bunniei see. PLLOUTGLOBAL is able to drive the global clock network directly?19:14
daveshahmight as well remove that global buffer, all it's doing is wasting a global and adding some skew to the pll output19:14
daveshahthe whole point of PLLOUTGLOBAL is it is a global network19:14
bunnieok cool.19:16
bunnieyep that fixed it19:16
bunniesorry, I come from xilinx land and typically a PLL output isn't useful without a BUFG behind it. thanks!19:16
daveshahObviously it shouldn't create that error either, but the global outputs of the PLL weren't being marked internally as clock output type ports, so timing analysis treated them wrongly19:20
daveshahBut I think, separately, a warning for this pattern would be useful (as globals are a scarce resource on the ice40)19:21
bunniedoes nextpnr also support the other PLL blocks like SB_PLL40_2F_PAD and what not?19:23
bunniealso, while I have you, even though I've constrained the clock I still get this : Info: Annotating ports with timing budgets for target frequency 12.00 MHz19:25
bunnieit correctly computes slack histograms from the clock of interest that is not at 12 MHz. Should I just ignore this or does this mean maybe I've missed some paths that should be constrained?19:25
felix_nats`: haven't gotten around to try to make litex work with zynq, but this might be worth a look:
tpbTitle: GitHub - cjbe/artiq-zynq: Proof-of-concept port of Artiq to Zynq (at
daveshahbunnie: All PLL types should supported19:28
daveshahThat 12MHz thing is a bad message, it should be removed19:28
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daveshahAt the end it will print all the clocks (and cross clock pairs if they exist) that it finds19:29
bunnieok thanks! I really appreciate the tips.19:29
bunnieOne thing that would be neat, but might be hard, would be to propagate clock constraints automatically through PLLs. Vivado is pretty easy that way for constraining a chip clock, you just corrcetly configure the input clock and all the derived clocks from PLLs are automatically annotated.19:31
daveshahI'm working on that19:31
daveshahWe actually do the most trivial case already, copying constraints 1:1 through global buffers19:31
bunnieoh neat. that will be nice. :) but for now, manual annotation is quite fine. I just need to figure out how to convince migen to output the name that nextpnr is picking for the clock.19:31
bunnielooks like easiest way to do it is to just put a "z" in front of any net alias that can confonud nextpnr, as it's resolving the chain alphabetically it seems. thanks! that would have taken me forever to figure out without the tip about how it picks the clock names.19:36
daveshahIt should be possible at some point to process net aliases properly in nextpnr, so it will accept any of the names19:36
daveshahYosys does tend to preserve them into the json at least19:37
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mithroewen: I realized I had a bunch of github issues at
tpbTitle: Issues · mithro/valentyusb · GitHub (at
ewenmithro: That's useful to know :-)20:58
ewenmithro: (I'm about to drive over to where you are.  Should be there in 10-15 mins.)20:58
mithroewen: Cool20:58
mithroewen: Test suite I was working on seems to pass now!20:58
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mithroesden: So it looks like prevents getting py.test working and checking all tests pass, etc21:55
tpbTitle: Split tests out into files · Issue #21 · mithro/valentyusb · GitHub (at
tpbTitle: Ubuntu Pastebin (at
mithroCarlFK: oh interesting, found one bug22:01
mithroCarlFK: Can you give a try?22:22
tpbTitle: GitHub - mithro/HDMI2USB-mode-switch at openocd-retry (at
ewenmithro: I'm assuming you meant me for issues/21?22:25
CarlFKmithro: checked out ... do you run mode-switch out of the working dir?  if so how?22:26
mithroCarlFK: yes I do22:26
mithroCarlFK: make conda; ./conda/bin/hdmi2usb-mode-switch I think...22:29
CarlFKmithro: ^^ and look at bad:  //
mithroCarlFK: try again... (git fetch mithro; git reset --hard mithro/openocd-rety)22:33
CarlFKmithro: tried, still bad:
tpbTitle: Ubuntu Pastebin (at
mithroCarlFK: getting closer though - try again now22:39
tpbTitle: Ubuntu Pastebin (at
tumbleweedmithro: can I send CarlFK over with an opsis?22:45
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CarlFKpavelow:  yes but no the screenshots aren't here looking...
tpbTitle: Xilinx Vivado · timvideos/litex-buildenv Wiki · GitHub (at
mithroCarlFK: ?22:52
tpbTitle: Xilinx Vivado screen shots · timvideos/litex-buildenv Wiki · GitHub (at
tpbTitle: Xilinx Vivado screen shots · timvideos/litex-buildenv Wiki · GitHub (at
CarlFKmithro: yes!22:53
mithroxobs: Did you see
tpbTitle: Tomu Fomu FPGA v0.0 support by osresearch · Pull Request #34 · tinyfpga/TinyFPGA-Bootloader · GitHub (at
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nats`to add the genesys 2 support I guess I have to add a platform file here: and a target directory here: ?23:41
tpbTitle: litex-buildenv/platforms at master · natsfr/litex-buildenv · GitHub (at
pavelowAny idea what's causing: OSError: no version directory for Xilinx tools found in /opt/Xilinx/23:48
pavelowwhen running `make gateware`23:48
CarlFKmithro: ^^23:57
mithropavelow: What is in your /opt/Xilinx ?23:58
mithropavelow: Do you have /opt/Xilinx/14.7 ?23:58
pavelowShould I?23:58
CarlFKI think same as me: /opt/Xilinx/Vivado/2018.223:59

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