Wednesday, 2019-01-02

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CarlFKmithro: do you know if bunny is coming to LCA?  and / or hackfest?05:45
xobsCarlFK: bunnie's not going to LCA this year.05:46
CarlFKxobs: aww.05:47
CarlFKxobs: someone here might come that wants to mess with pcb layout of something like Pink Zybo board to take off most of the stuff and make a little camera thingy05:49
CarlFKyou or anyone want to play with that ?05:50
xobsCarlFK: if I have time, perhaps.05:51
CarlFKneat - I wonder if there is room at the hackfest05:51
futarisIRCcloudCarlFK: Are you talking about the boards?05:52
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CarlFKfutarisIRCcloud: synaption[m] (standing here but not looged in)_ says "yes, well, but the Zybo is the one with the camera)05:59
futarisIRCcloudOh. Zybo Z7, I guess...06:03
CarlFKcould be - he left for the night06:59
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xobsmithro: The good news is that I can verify that the USB shift register works, mostly. The CPU can read packets, and can send packets, and both the CPU and my logic analyzer are correctly decoding things!09:15
xobsThe bad news is that the CPU isn't fast enough to do the MAC in software.09:15
cr1901_modernIs it running from flash?09:16
xobsNo, BRAM09:16
cr1901_modernuh oh...09:16
xobsI suspect the vexriscv interrupt latency is too long.09:16
xobsBut that's okay! mithro is working on a USB state machine, so this is a solvable problem.09:17
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mithroxobs: It would be good to understand the actual latency of VexRISCV interrupts09:52
mithroxobs: The SYNC byte doesn't end up in the input FIFO09:52
mithroxobs: But you do need the SYNC byte in the output FIFO09:53
xobsmithro: It would.  There are 18 instructions in the trap handler that execute before isr(), so that's certainly one source of latency.09:53
mithroxobs: 18!?09:53
xobsAnd I noticed that w.r.t. sync bytes. I added them in, and now I can NAK, though it's much too late for the host.09:54
tpbTitle: litex/crt0-vexriscv.S at master · enjoy-digital/litex · GitHub (at
mithroxobs: Yeah - but if you are successfully sending a NAK (even if too late), that is another good piece of the puzzle)09:56
xobsOh, sometimes I even send ACK packets.  Eventually. :)09:56
* xobs uploaded an image: image.png (56KB) < >09:57
daveshahI think at CCC we discussed that doubling the CPU clock frequency from 12 to 24MHz with some Yosys/nextpnr tweaks might be possible. I don't know if that would help10:00
xobsdaveshah: it wouldn't hurt! but I think the real solution is to do a state machine in verilog.10:02
mithroxobs: I have SOF packets...10:06
tpbTitle: Issues · mithro/valentyusb · GitHub (at
xobsmithro: they're so very plentiful, though! the nice thing is you can probably ignore them completely, unless we decide to do something with them later.10:08
mithroxobs: Yeah, it makes hard debugging when you want to trigger on a packet10:10
mithroInteresting ->
tpbTitle: Device-tree schemas [] (at
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mithroxobs: You still up, or did you go to bed already like a sensible person?16:51
mithroxobs: Did you get anywhere with the USB? I might start working on it again in ~2-3 hours16:54
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shornemithro: I am going to reply to the guy about nuttx21:22
shorneI have heard of it, I think its great, but really the OS support we listed is based on user/developer contributions21:23
shorneSo far the real support it Linux (expiramental) and the litex firmware21:24
shorneIs that right? have we really done zephyr support?21:24
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tpbTitle: iCEBreaker FPGA - 35c3 | Crowd Supply (at

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