Sunday, 2018-11-25

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futarisIRCcloudtinyfpga: looks good. When are the first prototypes expected? Happy to help out with the PCIe and/or USB3 bringup. I'm sure mithro, _florent_ and rohitksingh are also interested...02:48
tpbTitle: TinyFPGA EX | Crowd Supply (at
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mithrotannewt: so this is the interface so far;20:39
mithroThere is a 512byte buffer region which is memory mapped20:39
mithroEach endpoint has 3 csr registers20:39
mithroPointer into the buffer region20:40
mithroLength of packet20:40
mithroYou get an interrupt after a packet is sent or received20:41
tannewtthere is a shared region because pointer registers are expensive?20:41
mithrotannewt: and there is no guarantee that the rest of the memory can respond fast enough20:42
tannewtah, ok20:42
mithroThat is the bigger problem20:42
tannewtbecause the other memory is spram?20:42
mithroI can possible fix that with a FIFO in a future revision20:42
mithrotannewt: or external spiflash20:43
tannewtI just added a makefile to the tinyusb example:
tpbTitle: Add Makefile support for the cdc_msc_hid example by tannewt · Pull Request #15 · hathach/tinyusb · GitHub (at
tannewtthat sounds like a good start!20:43
mithroIt should be pretty easy to extend / change in the future20:44
mithroMy one concern is responding to requests on endpoint 020:44
mithroAs technically you are not suppose to NAK them...20:44
mithroThe core will NAK any requests on an endpoint until you rearm it after sending / receiving the packet20:46
tannewtI think thats why nrf has a dedicated 8 byte buffer for setup packets20:50
tannewtsince you know the size of those packets20:50
mithroThe buffering into ram isn't the issue, it's the reaponse20:52
tannewtjust always write to ram and always ack20:55
mithroNow I just need to get all the CDC stuff working20:59
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tannewtI'm gonna disappear to play games but I can help until then21:04
tannewtactually starting to write tinyusb porting instructions now21:04
mithrocr1901_modern: Could you take a look at ?21:06
tpbTitle: Two small fixes by mithro · Pull Request #128 · enjoy-digital/litex · GitHub (at
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cr1901_modernmithro: lgtm21:24
tpbTitle: Snippet | IRCCloud (at
mithrocr1901_modern: Any idea what I'm doing wrong here?21:44
cr1901_modernProbably missing a line like the following in your CRG():
tpbTitle: litex-buildenv/ at master · timvideos/litex-buildenv · GitHub (at
cr1901_modernIf it's not that, I don't know what's wrong21:51
mithrocr1901_modern: It seems to be coming from the UsbDeviceCpuInterface device...21:51
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cr1901_modernI can't know for sure without seeing the code. CRG as a submodule should've taken care of defining the sys clock domain21:52
mithrocr1901_modern: Do I need to do a self.clock_domains.cd_sys = ClockDomain() in my module if I have multiple clock domains?21:53
mithroIn the "available clock domains:" I see the crg_sys and usb_sys...21:54
cr1901_modernmithro: Again, I need to see the code21:54
cr1901_modernI don't know, clock domain handling is one of the pain points of migen21:55
tpbTitle: litex-buildenv/ at tinyusb-work · mithro/litex-buildenv · GitHub (at
cr1901_modernYes, you need "self.clock_domains.cd_sys = ClockDomain()" in your top level21:58
cr1901_modernIdk if "usb_sys" is because you did "self.clock_domains.cd_sys" in your USB core and migen's auto-naming kicked in, or you explicitly created a clock domain called "usb_sys"22:00
cr1901_modernmithro: Are usb_sys and crg_sys intended to be the same clock domain?22:02
cr1901_modernIf so, take out the "self.clock_domains.cd_sys" in your USB core and see what happens22:03
mithroNow I'm getting22:04
mithroTypeError: Expression of unrecognized type: 'ClockSignal'22:04
cr1901_modernI have no idea then. I would suggest showing sb022:05
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mithroThe issue seems to be my get_port on a memory22:08
mithro<migen.fhdl.specials._MemoryPort object at 0x7fc8eb7842e8> {'duid': 647, 'adr': <Signal adr at 0x7fc8eb777f28>, 'dat_r': <Signal dat_r at 0x7fc8eb784048>, 'we': <Signal we at 0x7fc8eb784128>, 'dat_w': <Signal dat_w at 0x7fc8eb784208>, 'async_read': False, 're': None, 'we_granularity': 0, 'mode': 1, 'clock': <Signal clk at 0x7fc8eb777860>}22:10
mithro<migen.fhdl.specials._MemoryPort object at 0x7fc8eb726080> {'duid': 1354, 'adr': <Signal adr at 0x7fc8eb722da0>, 'dat_r': <Signal dat_r at 0x7fc8eb722e48>, 'we': <Signal we at 0x7fc8eb722ef0>, 'dat_w': <Signal dat_w at 0x7fc8eb722f98>, 'async_read': False, 're': None, 'we_granularity': 0, 'mode': 1, 'clock': <migen.fhdl.structure.ClockSignal object at 0x7fc8eb7260b8>}22:10
cr1901_modernto ge the actual clock signal22:11
cr1901_modernget* even22:11
cr1901_modernalternatively, self.clock_domains.cd_sys.clk22:12
mithroI don't quite understand why one memory port is getting 'clock': Signal and the other one is getting 'clock': ClockSignal22:23
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