Thursday, 2018-11-15

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mithrotannewt: Hi!00:22
tannewthi hi @mithro00:22
tannewtI'm wrapping up a meeting atm00:22
mithroNo worries00:22
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tannewt@mithro ready when you are00:31
mithroOkay - won't be a moment00:31
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tannewtok, trying irccloud now02:48
CarlFKtannewt:  scroll down, "get it on goog play"02:52
tpbTitle: Home | (at
CarlFKpython -m SimpleHTTPServer 800703:49
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xobsDoes anyone happen to have any documentation on the ICE40 NVCM blocks?  Like (1) how do you program them, and (2) how does that state machine work?  I know it's OTP, but can you read the contents back?10:13
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xobsOh, apparently it's designed so you can't read it back.10:20
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xobsAnd I see a discussion mithro had ages ago about that very thing.12:10
daveshahYou can have a look at the SVF files that Diamond programmer can generater12:11
daveshahMy vague understanding is that you send an unlock command then treat it similar to a SPI flash12:11
daveshahbut I haven't ever looked in great detail12:11
xobs<xobs "And I see a discussion mithro ha"> Thanks, daveshah, that seems the easiest way to do it.12:13
daveshahIf you had an iCE40 to sacrifice, looking at the SPI commands with an LA over the wire would be reasonable too12:14
daveshahI thought I saw that there is some kind of verify command12:14
daveshahmaybe it is read-locked by a config bit rather than automatically12:14
xobsI'll have a few soon.12:15
mithroxobs: its programmed very much like programming spi - there is a document with diagrams and everythink12:16
xobsmithro: I see. I haven't found that document yet, just one that says to "contact Lattice"12:16
daveshahI'm pretty sure the secret unlock command isn't published12:17
daveshahnot that it's hard to discover either12:17
xobsFancy! Congratulations on the new boards.12:17
daveshahLooks awesome!!12:17
mithrowhat am I missing, why does the solder mask cover any of that middle region?12:19
mithroshouldn't I be seeing bare FR4 with traces?12:19
daveshahmithro: maybe the pcb fab "fixed" it for you12:25
mithrowell, that is what I'm wondering12:26
daveshahthey do have a tendency to mess with the soldermask layer12:26
mithroI actually think they may have used the paste layer?12:26
xobsYeah, ask for the check plots.12:26
mithroxobs / daveshah: but I'm right in expecting the middle to not have any soldermask?12:27
daveshahbased on the gerbers, yes12:28
xobsThey sometimes (read: often) change what you send them. The check plots are what they actually make, so they should give them to you.12:32
mithrowell, back to sleep for me12:49
cr1901_modernmithro: Did you make that yourself?12:50
felix_mithro: i wonder why the pads in the outer ring of pads for the fpga aren't round, but instead long like the pads for a qfn chip13:12
daveshahI'm guessing this is a trick to be able to route traces between them13:12
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mithrocr1901_modern: Do you have any more information on the spi flash sleep mode thingy?16:49
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cr1901_modernmithro: ICE40 will by default tell the SPI flash to power down after it loads the bitstream.17:02
cr1901_modernThere is a config bit (shared w/ warmboot/coldboot) that tells the FPGA to _not_ send the power down command17:02
cr1901_modernthis is basically required if doing XIP because the FPGA softcore will immediately try running insns from SPI flash. If powered down, the CPU will read garbage17:09
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mithrocr1901_modern: So flashing is very unhappy when you are building a gateware without a bios21:50
cr1901_modernmithro: Which board?21:52
mithrocr1901_modern: tinyfpga_bx21:52
cr1901_modernThat's excpected. The BIOS isn't embedded into the bitstream21:52
cr1901_modernyou must flash the gateware and the BIOS21:52
cr1901_modernyou can't just flash the gateware21:53
mithrocr1901_modern: This gateware doesn't have a bios, it just has the UART bridge21:53
cr1901_modernI don't know then21:53
ZipCPUIf you are working with the TinyFPGA BX, you'll want to use the tinyfpga tools to load your design21:54
ZipCPUthey get around the BIOS issue by loading the design at a separate starting address21:54
ZipCPUOnce loaded, the design then runs21:54
ZipCPUBut ... you can't load it at the zero address or you'll brick your board21:54
cr1901_modernI know for a fact the UART bridge has worked previously.21:55
mithroThe bridge works fine if I make a zero size bios file21:57
mithrocr1901_modern: The issue is that you are forcing the gateware to flash a bios, and this design doesn't have a bios...21:57
cr1901_modernI guess one of the makefile rules needs to be changed then21:58
ZipCPUWhat do you mean by BIOS?  Object code for a CPU?  Or the bitstream loader that's unique to the TinyFPGA BX?21:58
mithroZipCPU: Most LiteX SoC's have an embedded soft-cpu which initially boots to a bios that then loads the user firmware22:01
ZipCPUIf that's what you mean by BIOS, then okay, that makes more sense.22:03
tpbTitle: Snippet | IRCCloud (at
tpbTitle: Snippet | IRCCloud (at
cr1901_modernmithro: What is the exact error message you're seeing when trying to write out the bridge bitstream?22:15
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CarlFKmithro: where is the opsis power page you fixed?  really I want the usb header pinout22:19
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* CarlFK[m] uploaded an image: VectorImage_2018-11-15_044817.jpg (4666KB) < >22:54
* CarlFK[m] uploaded an image: VectorImage_2018-11-15_044902.jpg (98KB) < >22:55
CarlFKopsis usb to usb-a connector in C2 - fits perfectly22:56
CarlFKno idea if it works22:56
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mithroCarlFK: Your colorscheme could use a lot of improvement...23:24
CarlFKmithro: i used the wires I was handed to me - this is prototype23:26
CarlFKalso, I guessed at which way to hook it up and got it backwards.23:26
mithroCarlFK: Opps....23:26
CarlFKgood news: nothing fried. hooked up right, I got a console and all is well23:26
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CarlFKmithro: off to meet with Chris about KiCad conf - see ya23:31
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