Thursday, 2018-10-11

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shornemithro: a lot of people did :) btw, who are you cr1901_modern ?01:11
shorneunless you dont want to say01:11
shornemithro: the verilator sim was able to boot linux about half way01:12
shorneit was stuck on:01:12
shorne[    0.000000] Inode-cache hash table entries: 131072 (order: 6, 524288 bytes)01:12
shorne[    0.000000] Sorting __ex_table..01:12
shornefor about 8 hours, not really a good way to debug without a debug module01:12
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shornedoes anyone know of any litex/verilator debug module?01:12
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shorneif not I'll have a go at adapting this:
tpbTitle: orpsoc-cores/cores/verilator_tb_utils at master · openrisc/orpsoc-cores · GitHub (at
shornewe have a jtag server for use with openOCD01:13
shorneI think its just for trace, but its a start01:14
shorneI should probably just debug on my board... but I am just thinking about the flexibility of using this sim ...01:15
shorneok, need to go out now01:15
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cr1901_modernshorne: My real name is William, so grep for that lol04:34
cr1901_modernI can also be found very frequently wasting my life here:
shornecr1901_modern: I found it with just a search for cr1901, I realize you are the one porting MicroPython04:55
shornecan I just set FIRMWARE=micropython in litex-buildenv?04:55
cr1901_modernthen ./scripts/build-micropython.sh05:09
shorneoh, cool, not sure I saw this in the README / wiki yet05:13
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mithrocr1901_modern: Morning16:43
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mithroCarlFK: When do you get back from your conference travelling?16:52
CarlFKmithro: tues I think16:52
mithroCarlFK: Oh, that soon? I thought you were away for like a month or something!16:53
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maks_hello! I am Mithilesh. I am from India. My university is IIT BHU. I am new to the open source community. I am hoping to contribute significante to the organisation.19:29
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maks_I was setting up the environment for LiteX in my system. I got stuck at one point. It is asking for lisence file Xilinx.lic. A link is given for the to solve it. here is link ". But nothing is available there. Could someone help me?19:35
maks_sorry link is ""19:36
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cr1901_moderndaveshah: How are you compiling micropython for this? Is there a separate way to build micropython for picorv32 besides litex-buildenv?20:15
daveshahcr1901_modern: yes, I am using micko's work20:15
cr1901_modernOh right I forgot he did that20:16
tpbTitle: micropython/ports/picorv32 at master · mmicko/micropython · GitHub (at
cr1901_modern ._. That's... more than the amount of BRAM that ice40 FPGAs have20:18
tpbTitle: micropython/main.c at master · mmicko/micropython · GitHub (at
daveshahI don't know, that was what micko did20:19
daveshahThat was an UltraPlus to be fair20:19
daveshahBut it still leaves no room for stack or data20:19
cr1901_modernOh, UP has more BRAM than even the hx8k?20:20
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daveshahcr1901_modern: that example used all the SPRAM20:26
daveshahOf which there is 128kB20:26
cr1901_modernOh nevermind20:27
cr1901_modernright 0x20000 == 128kb, not 32kb. I can't count.20:27
cr1901_modernGod I am in a rut this week20:27
felix_daveshah: ooh, very nice (the picorv32 on ecp5 with open toolchain)20:29
daveshahBRAM initialisation is still a bit temperental. But other than that things on the ecp5 side are going pretty well20:30
rohitksinghdaveshah: congrats on the exceptional progress with ECP5 RE! saw your tweet and it looks like ECP5 support is coming earlier & faster than previously anticipated! :)20:40
rohitksinghmaks_: you need to install Xilinx Vivado/ISE (depending on FPGA being used/targeted). Vivado should automatically generate a free license file IIRC. For ISE you need to download license from Xilinx website after registering20:43
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mithrocr1901_modern: poke?23:20
mithrohey daveshah!23:20
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