Sunday, 2018-09-30

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shorneI think I am going to have to bisect this issue, we know it was working last year.  Maybe its qemu.00:09
shorneI debugged it but its something stange happening in ioremap for the UART00:09
shornewhich is the only ioremap we really need to do00:10
Tobacr1901_modern: hey are you on? Tim says to poke you about micropython00:10
TobaI am trying to understand how to improve the memory availability for of the FuPy Arty A700:11
cr1901_modernToba: I've yet to try FuPy on the Arty, tbh. Tim's gonna have to be more specific- aren't we already running Micropython from DRAM anyway on that board?00:12
Tobayes but the stack appears to be mapped to sram00:13
Tobaand I don't know how micropython figures out where to put its heap00:13
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cr1901_modernHmmm, running out of sram?00:16
mithrocr1901_modern: See Toba mention, it seems like micropython is using the sram for the stack / heap00:17
mithrocr1901_modern: But running from DRAM00:17
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cr1901_modernmithro: Yes, that's because of of this line:
tpbTitle: micropython/litex.ld at master · fupy/micropython · GitHub (at
cr1901_modernChange "sram" to "main_ram" and that will move your stack to DRAM00:18
mithrocr1901_modern: Yes, that is where we got too :-P00:18
mithrocr1901_modern: And now Toba is learning about linker scripts :-P00:18
cr1901_modernSo what's the problem then? :P00:18
cr1901_modernDo you want me to give a tutorial on linker scripts or something?00:19
Tobano, I think you've answered the question00:20
cr1901_modernToba: You may wish to move .bss to main_ram as well for consistency;.00:23
Tobayeah it already is in the branch I'm on00:23
TobaI'm on master00:23
Tobaof micropython00:23
Tobathe master of this repo //
cr1901_modern It's not on my copy00:24
tpbTitle: micropython/litex.ld at master · fupy/micropython · GitHub (at
Tobaoh wait no it's not, I already had done that00:24
Tobabecause it seemed like I should00:24
tpbTitle: main_ram vs sram - (at
Tobabut isn't this going to try to put the stack at the same part of RAM that the micropython code is already being loaded into00:25
Tobado I need to align it differently? I'm not really sure what PROVIDE(_fstack really means00:25
TobaI guess that's just defining _fstack?00:26
cr1901_modernYes, it's defining _fstack at the very end of main_ram00:26
cr1901_modernand it's subtracting 4 because the CPUs that micropython use have a stack that by convention points to the "next free slot"00:27
Tobaand the lm32 cpu is 4 byte aligned?00:27
cr1901_modernthe ABI wants the stack 4 byte aligned, yes00:28
Toba so it's already counting memory down ward in the stack anyways? Is the system smart enough to not smash the stack into the space allocated by the linker?00:28
tpbTitle: Using LD, the GNU linker - Command Language (at
Tobaand I shouldn't need to use MEMORY to do this?00:28
Tobasorry for the stray link, I was going in that direction before you pointed out it's happening at the very end of main_ram - by end I assume you mean the high end of the addresses?00:29
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cr1901_modernmithro: Btw, the Opsis HDMI2USB firmware has captured plenty of conferences; the sram wouldn't be nearly enough for global buffers. How does the HDMI2USB handle this?00:29
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cr1901_modernToba: LiteX handles defining memory regions00:29
cr1901_modernyou can see this under software/include/generated/regions.ld00:30
Tobaoh I was wondering where the generate folder is00:30
Tobasince that is INCLUDEd by the litex ld00:30
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cr1901_modern>Is the system smart enough to not smash the stack into the space allocated by the linker00:32
cr1901_modernThe linker can detect overlapping regions, and whether globals don't fit into a region. But it can't really say much about stack usage b/c that's unknown until runtime. You just PROVIDE it a var where the stack starts and hope for the best.00:32
cr1901_modernThe startup code will take that value of _fstack and initialize the stack pointer00:32
Tobaso there's no way to tell micropython where to put the brakes on and stop trying to put things onto the stack?00:32
Tobawhat about the python heap?00:33
mithrocr1901_modern: The frame buffers are stored in DDR ram00:33
cr1901_moderncr1901_modern: How do you enforce that if .bss is pointing to sram?00:34
cr1901_modernToba: I don't think micropython is designed to do that, no. I guess in principle you could add that and micropython could check.00:35
cr1901_modernmithro: How do you enforce that frame buffers are in DDR RAM if .bss is pointing to sram?00:35
mithrocr1901_modern: The frame buffers just write to a random memory location00:37
tpbTitle: litex-buildenv/framebuffer.h at master · timvideos/litex-buildenv · GitHub (at
cr1901_modernWell... that's one way of doing it :P00:38
mithrocr1901_modern: It's bare metal C, all bets are off :-P00:40
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tpbTitle: Fix the framebuffer allocations · Issue #250 · timvideos/HDMI2USB-litex-firmware · GitHub (at
TobaI kind of think the problem is the heap not the stack00:41
Tobasince the errors I'm getting are gc ones00:41
TobaHm, I guess it's not errors so much as gc debugger output.00:42
cr1901_moderngc output is normal00:42
cr1901_modernif gc failure happens, it'll say so :P00:42
Tobaah yes there is good old MemoryError00:43
cr1901_modernAre you getting those or not?00:44
TobaI was able to get one pretty easily, the entire heap appears to be 1984 bytes00:44
TobaGC: total: 1984, used: 1296, free: 68800:44
cr1901_modernYea something seems grossly wrong with that00:44
cr1901_modernIdk right now :P, sorry :(00:45
Tobais master the branch of micropython to be using here00:45
TobaI mean is that where all the latest development code is for the fupy port00:46
Tobabecause I would hate to be duplicating effort00:46
cr1901_modernyes, afaik00:46
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mithroToba: ewen who doesn't seem to be here at the moment might know more00:47
cr1901_modernToba: Found the culprit
tpbTitle: micropython/main.c at master · fupy/micropython · GitHub (at
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cr1901_modernAssuming MICROPY_ENABLE_GC is, well, enabled (Idk if it is)00:50
cr1901_modernBut heap[2048]; is gonna be put into BSS00:50
Tobaah yes in main.c00:55
Tobathat would do it00:55
Tobaand bss is in main_ram now on my copy00:55
Tobaso I just need to make this bigger and rebuild00:55
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cr1901_modernRight. Probably a better solution is to size it based on how large regions.ld is, but Idk a nice way to do that without relying on _fbss or linker provided variables00:56
cr1901_modern(IMO only the startup code should need to access those)00:56
cr1901_modernWe can probably use SRAM_BASE/MAIN_RAM_BASE for this01:00
cr1901_modernchar heap[3*SRAM_SIZE/4]; for instance (25% left)01:02
cr1901_modernToba: I need to rest for tonight, but hope that helps a bit :)01:04
TobaI just hard coded it to 192 mb01:05
Tobasince IIRC there is 256 mb on the chip on the arty a701:06
cr1901_modernWell that's gonna break my tinyfpga port, which has... 10kB of SRAM? ;)01:06
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TobaOK, I see what you mean if I try to make a PR or something I will be more reasonable about it01:06
cr1901_modernBut fair enough01:06
Tobathat is a good point about just picking 75% - is there a good place to put end-user configuration stuff01:06
Tobasuch that someone rolling a micropython firmware could make their own decision and configure it?01:07
cr1901_modernI don't think so right now. Maybe it should be configured as an attribute per FPGA platform.01:08
cr1901_modernthat generates a constant into software/include/generated/csr.h or something01:08
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CarlFKpzieba[m]: hi!02:41
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tpbTitle: NeTV2 | Crowd Supply (at
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shornewell, I switched to the old version of qemu, still same issue but at least debugging works better now.  Something with recent MMU changes broke gdb07:12
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shorneoh, and with better logging and a quick hack kernel boots07:31
shorneso... I am not sure what changed,  I updated early con from using a 4K IO range (which was causing overflow in ioremap) to a 256 byte iorange07:33
shorneand everything works fine07:33
shorne[    1.570000] Freeing unused kernel memory: 3168K07:33
shorne[    1.570000] This architecture does not have kernel memory protection.07:33
shorneStarting logging: OK07:33
shorneInitializing random number generator... done.07:33
shorneStarting network: OK07:33
shorneStarting dropbear sshd: OK07:33
shorneWelcome to Buildroot07:33
shornebuildroot login:07:33
shorneWe didnt have to do this hack before07:34
shorneCarlFK: I am posting 2 patches to
shornethat should fix the linux boot07:50
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mithroshorne: Great!12:37
mithrocr1901_modern: Did you end up adding a "lite" target for the vexriscv?12:38
mithrocr1901_modern: And did those boards turn up?12:39
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mithronrossi: How goes meta-hdl layer?12:58
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mithroshorne: Yay! It seems to work for me in qemu!13:06
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cr1901_modernmithro: >Did you end up adding a "lite" target for the vexriscv? Yes, but it's not really tested13:15
cr1901_modern>And did those boards turn up? Yes, sorry, forgot to mention :P13:15
mithrocr1901_modern: It doesn't exist in litex yet?13:21
mithrocr1901_modern: Or do I need to roll third_party again?13:21
mithrocr1901_modern: FYI ->
mithrocr1901_modern: Much greeness :-P13:21
mithroGoing to find breakfast with CarlFK now13:22
mithrocr1901_modern: This might be the most interesting for you ->
mithroC=picorv32 P=tinyfpga_bx F=stub T=base13:23
cr1901_modernmithro: My branch for vexriscv litex isn't pushed yet.13:23
cr1901_modernI've been busy the last few days, but let's see if I can't finalize the tinyfpga stuff today13:24
cr1901_modernat present, when I pulled LiteX to the most recent commit, I managed to break the firmware13:24
cr1901_modernthe micropython* firmware13:24
cr1901_modernAlso, cool picorv32 works :P13:25
mithroNo idea if it boots, but it builds13:25
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cr1901_modernmithro: Are you around?15:33
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cr1901_modernIt's time to merge in tinyfpga micropython:
tpbTitle: firmware: Update litex submodule, Makefiles, and linker scripts to support crt0-flash startup code. by cr1901 · Pull Request #67 · timvideos/litex-buildenv · GitHub (at
tpbTitle: Add support for LiteX boards which run their main program from flash. by cr1901 · Pull Request #51 · fupy/micropython · GitHub (at
cr1901_modernBoth are these are safe to merge IMO15:36
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cr1901_modernToba, mithro: Referencing linker-provided vars inside main.c isn't personally my favorite thing to do, but we should probably do something like this to set up heap space
tpbTitle: micropython/mk20dx256.ld at master · fupy/micropython · GitHub (at
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mithrocr1901_modern: I'll merge it after I confirm my stuff works16:23
cr1901_modernmithro: Excellent, I'm looking up info about the single port RAM now. It's definitely fine for system memory, but granularity is low; there's essentially only 4 RAMs in a up5k device16:26
cr1901_modernI'll probably just make a wishbone Migen wrapper that instantiates it. Probably should go under LiteX cores?16:26
cr1901_modernAlternatively I could add arty-s7 support, which is simple enough for an afternoon16:29
cr1901_modern(I think)16:29
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cr1901_moderndaveshah: There's no passes in yosys currently that handle the single-port RAM, correct?16:42
daveshahcr1901_modern: no, unfortunately not16:43
daveshahThis will soon be a higher priority to me, as the same code would also be used to handle true-dual port RAMs in ECP5 and Xilinx16:43
cr1901_modernThat might actually be good in my case; I don't want "RAM used by cache/peripherals" to accidentally be put into single-port RAM16:43
daveshahYes, on the iCE40 it's usually fine to control SPRAM use anyway16:43
cr1901_modernI'm prob gonna create a wishbone SP_RAM interface which supports only 32-bit width and either 16k or 32k depth16:45
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Tobacr1901_modern: I follow you, kinda. I might be able to get that to work.17:17
Tobacr1901_modern: So in mk20dx256.ld, line 171 is defining the HEAP_END - that's what assigning to a linker var that starts with an _ does?17:19
cr1901_modernToba: No, _heap_end appears to be unused in main.c17:21
cr1901_modern The person who wrote the linker script opted to define _heap_end, but HEAP_END is actually defined here17:22
tpbTitle: micropython/main.c at master · fupy/micropython · GitHub (at
Tobawell you said it was using linker-provided vars17:23
TobaI guess _heap_start is the one you meant17:23
Toba(slaps forehead)17:23
cr1901_modernyes, by "vars" I meant one or more, sorry :P17:23
cr1901_modernIt's not _wrong_ to reference linker vars in main.c, I just don't like it :)17:24
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CarlFKshorne: Toba: woot!  qemu # cat /proc/cpuinfo17:51
CarlFKcpu: OpenRISC-017:51
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CarlFKshorne: linux on qemu boots, same on arty stuck at the same: Executing booted program at 0x4000000018:13
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TobaCarlFK: does it basically not provide you any way to know if it's working beyond that point?18:22
CarlFKToba: 'yes'18:22
Tobadoes it normally offer open ports over ethernet or something and that's how you would know it's working?18:23
CarlFKToba: same visual as when it wasn't working with qemu, and shorne was mumbling "device tree"18:23
TobaI know some of those words.18:23
CarlFKI leanred a bit about it on my way to bean and bagel this morning18:24
CarlFKmy guess is the arty device tree isn't (additive)ly (verb)18:25
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CarlFK  [FLTERM] Booting the device... Executing booted program at 0x4000000018:26
tpbTitle: Ubuntu Pastebin (at
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cr1901_modern_florent_: In arty a7 platform file, why are the cd_sys4x and cd_sys4x_dqs configured as reset_less?20:01
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CarlFKshorne: Toba: woot!!! on Arty!!! # cat /proc/cpuinfo20:19
CarlFKcpu architecture: OpenRISC 1000 (1.1-rev0)20:19
tpbTitle: History of the Project · timvideos/HDMI2USB Wiki · GitHub (at
TobaCarlFK: neato20:30
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CarlFKtwo linuxs booted!!!20:59
Tobaat once?21:00
Tobadid you put 2 soft cpus on in the fpga at once?21:01
Tobathat could be pretty cool21:01
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shorneCarlFK: did you change anything to fix arty?21:42
CarlFK[m]Toba  no Peter got his working also21:55
CarlFK[m]<freenode_sho "CarlFK: did you change anything "> shorne just ran the install and build and run Scripts21:56
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mithroIt's green!22:35
mithroCarlFK: 340 should be there now22:39
cr1901_modernmithro: Awesome, can we try merging my stuff next :)?22:43
mithrocr1901_modern: when I get into the air, I plan to merge the LiteX roll22:44
cr1901_modernAlright then. I am clearly not being productive today, so I'm gonna take the rest of the day off :P22:44
cr1901_modern(what's left of it anyway)22:44
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cr1901_modernmithro: Hopefully the damn thing _stays_ green this time22:51
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cr1901_modernmithro: Please don't like your own tweets :P22:58
mithrocr1901_modern: why not? Someone has too :-P22:59
cr1901_modernIt's a pet peeve of mine when others do it. Ditto for when ppl fav their own github repositories22:59
cr1901_modern(which of course friends have done on purpose anyway b/c they know I hate it)22:59
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cr1901_modernWhat happens when litex-buildenv reaches 200 supported configurations :P?23:07
cr1901_modernAlso is vexriscv currently not being build?23:08
cr1901_modernoh nevermind23:08
cr1901_modernI missed it23:09
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CarlFKmithro: off to a good start - 340 boots: git describe: v0.0.4-340-g3fb4e7c23:38
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