Friday, 2018-09-07

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shorneCarlFK: I was out yesterday00:21
shornechecking ...00:21
shorneCarlFK: its saying, assert len(bios_data) < make.BIOS_SIZE00:23
CarlFKshorne: mithro came up with a good plan for the include <> and I may have that working:00:23
shornehow big is the build/arty_net_or1k//software/firmware/firmware.fbi that got generated00:23
CarlFK CFLAGS=" \00:24
CarlFK -I$TOP_DIR/third_party/litex/litex/soc/software/include" \00:24
shorneI think its saying to bigger than the BIOS_SIZE i.e. wont fit on the board00:24
shorneCarlFK: right, using -I will work, but since the hw/common.h was in qemu, the qemu way is to use -iquote00:25
CarlFKshorne: but mithro said it will break something else00:25
shorneanyway... we need a solution for including/overriding the csr.h files00:25
shorneyeah, I think it will be OK for now to get it working00:26
shorneI think we need something else when upstreaming... just thinking about that part00:26
CarlFKhttps://mail.google.com/mail/u/0/#inbox/FMfcgxvzKQrNLcDBjbpVSCXlMFSWjnvd00:29
tpbTitle: Gmail (at mail.google.com)00:29
CarlFKderp00:29
CarlFKhttps://github.com/timvideos/litex-buildenv/issues/4900:29
tpbTitle: qemu complier flags changed, #include needs to be "" · Issue #49 · timvideos/litex-buildenv · GitHub (at github.com)00:29
shorneI see00:37
CarlFKshorne: back on filesize: 75556 Sep  6 17:00 build/arty_net_or1k//software/firmware/firmware.fbi01:07
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futarisIRCcloudhttps://github.com/benfred/py-spy looks pretty nifty01:42
tpbTitle: GitHub - benfred/py-spy: Sampling profiler for Python programs (at github.com)01:42
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mithroCarlFK: I feel dejavue with https://github.com/timvideos/litex-buildenv/pull/47/files -- I'm sure I did exactly that change previously...02:18
tpbTitle: implement QEMU_REMOTE and QEMU_BRANCH. and CPU=or1k by CarlFK · Pull Request #47 · timvideos/litex-buildenv · GitHub (at github.com)02:18
CarlFKmithro: welp, I tripped all over it trying to set vars to use shorne's repo/branch02:19
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shorneCarlFK: mithro: fwiw the change looks good to me03:07
mithroCarlFK: that git pull is bad03:09
CarlFKmithro: I was wondering about that03:09
mithroBack to writing emails for me...03:16
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shorneah, I missed, yes fetch, since we checkout later05:47
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xobsHooray, just submitted a PR for CSR support in openocd-vexriscv.  Now it's /actually/ possible to do things like investigate whether IRQs are enabled.06:03
xobsRelatedly: rasm2 (from radare2) is a fantastic resource.06:04
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cr1901_modernWhen it works, which is not usually, r2 is a good tool07:17
cr1901_moderntinyfpga: --program-image just disables the checks that you're within program/user data region, _except_ for the bootloader check, correct?07:28
tinyfpgacr1901_modern: it makes sure your image is contained within the beginning of the user image area and the end of the user data area07:30
tinyfpgacr1901_modern: it should complain if you try to program outside that area07:31
cr1901_modernexcellent. Then I'll update migens tinyprog class as follows:07:31
cr1901_modernIf addr passed in is None, use "-p" if user_data=False, "-u" if user_data=True07:31
cr1901_modernotherwise addr is not None, so use "--program-image"07:32
cr1901_moderndoes that sound reasonable?07:32
cr1901_moderntinyfpga: ^^07:33
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tinyfpgacr1901_modern: yeah, that sounds reasonable...I could take a look at it when you submit the pull request or you have it pushed to your GitHub repo07:54
cr1901_moderntinyfpga: I'll push it in 2 mins literally :P07:58
cr1901_modernI think07:58
cr1901_modernMake that 5 minutes while Atom loads itself from swap07:59
cr1901_moderntinyfpga: https://github.com/cr1901/litex/commit/c812321a937c95abed5b233619d8043fcae7c1a508:12
tpbTitle: lattice/programmer: Use --program-image option with tinyprog if addre… · cr1901/[email protected] · GitHub (at github.com)08:12
cr1901_modernOr rather, here: https://github.com/cr1901/litex/blob/c812321a937c95abed5b233619d8043fcae7c1a5/litex/build/lattice/programmer.py#L64-L8708:12
tpbTitle: litex/programmer.py at c812321a937c95abed5b233619d8043fcae7c1a5 · cr1901/litex · GitHub (at github.com)08:12
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xobsIn litex, how do I request a connector?09:54
xobsI'm trying to map pins on the Arti "pmoda" to a GPIO block, but platform.request("pmoda", 0) gives me a "Resource not found" error.09:54
xobsI've also tried platform.request("V14") to e.g. get one random pin from pmodc.10:29
xobsHmm... I'm getting somewhere.  I can try platform.constraint_manager.connector_manager.resolve_identifiers(["pmoda:0"]) and get an error that "G13 ... is not a Migen value", so I'm at least able to go from a connector name to a pad name.10:39
cr1901_modernxobs: plat.add_extension([("foo", 0, Pins("CONNECTOR_NAME:0 CONNECTOR_ NAME:1"))])10:41
cr1901_modernthen plat.request("foo")10:41
xobscr1901_modern: These pins are already part of _connectors[].  Do I have to add them again?10:42
xobsOr I suppose I could pull the pads out by iterating through platform.constraint_manager.connector_manager.resolve_identifiers("pmoda:X") and building them into a string, then passing them to platform.add_extension().10:43
cr1901_modernxobs: No, the syntax "CONNECTOR_NAME:[0-9]*" within Pins() constructor is reserved precisely so you don't need to add the pins again10:43
cr1901_modernOr do I misunderstand what you're asking?10:44
xobsOhh, so I need do: platform.add_extension([("pmoda", 0, Pins("pmoda:0 pmoda:1 pmoda:2 pmoda:3 pmoda:4 pmoda:5 pmoda:6 pmoda:7"))]) before I do platform.request("foo")?10:44
cr1901_modernyes10:44
cr1901_modernGrep for "my_i2c_device" in my blog post for another example: https://www.wdj-consulting.com/blog/migen-port.html10:45
tpbTitle: WDJ - migen-port (at www.wdj-consulting.com)10:45
cr1901_modernxobs: a PMOD helper library for migen/litex (miconn) was in my plans to make it easier to attach PMODs, but b/c I haven't figured out how to clone myself I haven't gotten around to it10:46
xobsI see, thanks.  Now I'm adding all of those pins into a single `pmod` connector, and it seems to be doing the right thing.11:02
xobsI have to add another parameter IOStandard("LVCMOS33"), because on Arty it's on the same bank as the Ethernet, at it appears to default to the 1.5V domain otherwise.11:25
cr1901_modernright I omitted that, sorry. That works too. But why does it default to 1.5V?11:29
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xobsI'm not sure.  Maybe it just picks a random domain?11:30
cr1901_modernis Ethernet 1.5V domain?11:30
cr1901_modernI thought 100MB Ethernet used 3.3V...11:31
* cr1901_modern doesn't actually know for sure11:31
xobsEthernet is in the 3.3V domain.  Maybe 1.5V is DDR?11:31
cr1901_modernMainly asking b/c you said: "because on Arty it's on the same bank as the Ethernet, at it appears to default to the 1.5V domain otherwise."11:32
cr1901_modernAnd b/c I went to bed at 9 and woke up at 12, I'm inferring a cause and effect relationship11:32
cr1901_modernbetween Ethernet and 1.5V11:32
xobsI think the error is that it's defaulting to 1.5V, but PMODA:0 and one of the Ethernet pins share an IO bank, and the Ethernet pin is at 3.3V, hence the error.11:33
cr1901_modernahhh11:33
cr1901_modernthat sounds logical11:33
cr1901_modernin any case yea, adding IOStandard works just fine. I omitted it for the sake of keeping the example minimal :)11:34
cr1901_modernIdeally I would implement that PMOD library11:34
cr1901_modernand ask ppl to help me11:34
cr1901_modernxobs: Which PMOD, out of curiosity11:50
xobsAll of them. It gave 0, 16, and 24 as examples.11:52
cr1901_modernxobs: I meant the actual PMOD module :P11:53
cr1901_modernand examples?11:53
cr1901_modernwhat tutorial are you using?11:53
xobsOhhh. No tutorial. I'm trying to import a gpio module into litex so I can access it from Wishbone.11:57
xobsI can tell you about it more later. I just left the office.11:57
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xobscr1901_modern: I'm doing what lots of others want to do -- an SoC.  At the very least, I'll need a GPIO block.  Maybe a SPI and I2C block.  Then eventually it would be nice to have an IOMUX in front of it all.13:54
xobsBut for now I'm still getting familiar with litex.  Hence doing "simple" projects like integrating a wishbone GPIO block.13:55
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shorneCarlFK: did you fix the 'assert len(bios_data) < make.BIOS_SIZE' failure?15:53
shorneI am also getting it, bios is about 34k, but max size allowed is 32k15:53
CarlFKshorne: no - do we know what needs to be done?15:53
shorneCarlFK: it seems we need to trim some code15:54
CarlFKshorne: mine is   75556 Sep  6 17:00 build/arty_net_or1k//software/firmware/firmware.fb16:02
shorne-rw-rw-r--. 1 shorne shorne 163300 Sep  7 20:44 build/arty_net_or1k/software/bios/bios.elf16:03
shorne-rw-rw-r--. 1 shorne shorne  34288 Sep  7 20:44 build/arty_net_or1k/software/bios/bios.bin16:03
shornethis is the bios file that causes the assert failure16:03
shornebine is 34k16:03
shorne"mine is 34k"16:04
shorneI added some prints to the mkimage.py to understand which file caused the assert failure16:04
CarlFKok, that one is 34288  too16:08
shornehmm, seems like there has been a lot of work on it recently16:14
shornei.e. sdram.o16:17
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CarlFKshorne: who did work on it last?16:30
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shorne_florent_: seems to have been working on it16:35
shorne_florent_: it seems bios.bin has passed the 32k limit on OpenRISC ^ (Maybe due to new commands or the sdram work?)16:36
shorneCan we either, do any refactors to reduce code size, or change the limit of 32k?16:36
CarlFKshorne: do you know why the limit is 32k?17:50
CarlFKlike, is it because something won't work, or trying to manage resources17:51
CarlFKwhat is the verb to describe what we are doing with this qemu code and scripts?   migrating, porting, recovering?  what is the opposite of bit-rot?18:11
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CarlFKshorne: is this that? https://github.com/timvideos/litex-buildenv/issues/4318:55
tpbTitle: or1k bios is too large to fit in ROM region · Issue #43 · timvideos/litex-buildenv · GitHub (at github.com)18:55
CarlFKtac-tics: or1k = Open RISC 1000.  thus my .. um.. something.  fix all the bugs please thank you.18:55
tac-ticsindeed18:56
tac-ticswat18:56
CarlFKmithro: where is the spreadsheet of fpga board survey you wanted filled in? (that I saw now has a nexis-video row)19:01
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mithroCarlFK: https://github.com/timvideos/litex-buildenv/wiki/Boards23:40
tpbTitle: Boards · timvideos/litex-buildenv Wiki · GitHub (at github.com)23:40
CarlFKmithro: spreadsheet - google doc.  lots of color coded cells23:41
mithroCarlFK: Go to that page23:42
CarlFKah that's a link23:42
CarlFKmithro: can you .. freeze I think it is called, the first column: "Code"23:44
CarlFKso that when I scroll it stays visible23:44
mithroCarlFK: Hrm, it's already frozen in the edit view23:45
CarlFKswell :p23:45
CarlFKnever mind, not that importatn23:45
CarlFKnexys_video has Artix 7 - should the lca linux build scripts work?23:46
mithroCarlFK: I added an "Edit" link23:46
CarlFKmithro: weird.  I was going to ask to freeze the column headers too, but yeah, they are in edit mode. someone should log an issue somewhere :p23:48
mithroCarlFK: I think it's because I linked to the "published" version...23:48
mithroCarlFK: Yes, the nexys_video should work with the Linux stuff23:48
CarlFKmithro: tac-tics has a nexys_video and said "what should I do?"  so I am trying to give him something to do.23:49
mithroCarlFK: I thought he had a Nexys 4 DDR?23:49
CarlFKtac-tics: A) what do you have? and B) did you download the 20+ gig of tarball?23:50
mithrocr1901_modern: How is the ice40 SoC going?23:51
CarlFKmithro: i'm blocked testing the PR, I think because of  https://github.com/timvideos/litex-buildenv/issues/4323:51
tpbTitle: or1k bios is too large to fit in ROM region · Issue #43 · timvideos/litex-buildenv · GitHub (at github.com)23:51
mithroCarlFK: which platform are you building for?23:52
CarlFKmithro: well... prompt says: (LX P=arty C=or1k)   but I think I am trying to build qemu23:54
mithroCarlFK: The line you need to fix is https://github.com/timvideos/litex-buildenv/blob/master/targets/arty/net.py#L31 then?23:54
tpbTitle: litex-buildenv/net.py at master · timvideos/litex-buildenv · GitHub (at github.com)23:54

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